---
# System prepended metadata

title: ASOC LAB4
tags: [SOC]

---

ASOC LAB4 logbook
1. 缺少bin2coe
    1. 先安裝pip
    2. `pip3 install bin2coe`
2. 找不到pynq-z2
    1. 安裝board file
    2. ~~將安裝path加入init.tcl~~ ( deprecated: 好像改成其他名字了)
    ref: https://support.xilinx.com/s/question/0D52E00006hpa6VSAQ/search-path-for-board-files?language=en_US


# 將fir加入tcl檔

# config fir 
bug in fsic
https://github.com/bol-edu/HLS-SOC-Discussions/discussions/214#discussion-6606112


---

啟動vitis的指令:
```shell=
source ~/vitis.sh
vitis_hls
```

:::warning
不要直接把vitis.sh加入.bashrc，因為裡面有他們自己版本的cmake，會跟平常用的cmake混在一起
:::





# fpga emulation
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/caravel_ps_0/mprj_out
-> 看起來應該沒事，應該是因為這個module原本不是專門為了用在這個地方設計的，所以這裡多出了沒用到的pin





