---
# System prepended metadata

title: low power design
tags: [SOC]

---

# low power design

常見的low power design有4種方式

## clock gating
- 有50%或更多的dynamic power是花在clock buffers上
    - clock buffers在整個系統中有最高的toggle rate
    - 系統中有大量的clock buffers
    - 為了降低clock delay，clock buffers通常是high drive strength
- 即使輸入和輸出維持不變，有接收到clock的flip-flop還是會消耗dynamic power
- 為了省電可以在不需要的時候把clock關掉
- 現代的libraries中有特定的clock gating cells，eda工具能分析設計並自動插入clock gating cells，不需要更改rtl code

## multi-voltage
- 把soc分成幾個power domain，不同區域使用不同電壓
- critical path用高電壓，其他地方用低電壓
- 訊號要跨過不同power doamin時需要level shifter
    - 把level-shifter放在接收domain
    - low-to-high level shifters有較大delay，在做timing critical blocks的RTL design時要先考慮清楚
    - 不同domain間的電壓關係要定清楚，這樣eda工具才能判斷要用up-或down-shifter

## multi-vt
![圖片](https://hackmd.io/_uploads/HkgP3tK8A.png)
![圖片](https://hackmd.io/_uploads/HycP3tK8C.png)

## power gating
#### power switching cell: header vs. footer
Power switch cell可分為footer跟header兩種類型。Footer是透過開關vss來操控邏輯閘的電源，而header則是透過開關vdd來操控邏輯閘的電源。一般只會選擇使用其中一種，不會兩者同時使用，以此減少IR drop。如果有external power gating或是多個power rails的話，header switch會是比較好的選擇。
#### Power Gating Challenge
- Managing the in-rush current when the power is reconnected - Staggered
- Design of the power switching fabric 
- Design of the power gating controller
- Interface isolation - use of retention registers and isolation cells
- Minimizing the impact of power gating on timing and area.
- The functional control of clocks and resets 
- Developing the correct constraints for implementation and analysis
- Performing state-dependent verification for each supported power state
- Performing power state transition verification to ensure all legal state entry and exit arcs are simulated and verified
- Developing a strategy for manufacturing and production test

## 其他
![圖片](https://hackmd.io/_uploads/BJ5iJYFLR.png)
![圖片](https://hackmd.io/_uploads/Syt3ktKIC.png)

