---
# System prepended metadata

title: Report of I understood
tags: [DeWei, Discussion]

---

# Report of I understood

## 1 Compile

### 1.1 Has error when I compile with original files

![](https://i.imgur.com/2oJRgva.png)

### 1.2 Solution (I thought may not correct)

Comment here in the file `roc_top.pdc`
(`.pdc`file is physical constrain file)

![reference link](https://i.imgur.com/jY1Lfvh.png)

### 1.3 Note 

* This project files is fine when compiled from jp?
* Actually, developes have done a lot of effort for *constrain*, see `roc_top.pdc`
* Project seems to have build problems 

## 2 Problem about roc-block
* IP? HDL?

## 2 Architecture of program

* Top
  * PLL
  * IO Buffer
  * ROC-Block (?)

## 3 My thoughts on clock dividers

### Ideas: Cascade PLL

* One PLL Blocks can output 6 phase of clock
* Officical doc (CCC Blocks) 
  * ![](https://i.imgur.com/afpk5CC.png)
* See these picture, I can't guarantee output path will be same when cross block
  * ![](https://i.imgur.com/ksu3qgc.png)


### 3.2 Why we needs PLL

Because the path of PLL output clock has been aligned

[Refer to here](https://ewh.ieee.org/r5/denver/sscs/Presentations/2007_05_Fischette.pdf)

###### tags: `Discussion` `DeWei`