關於 Vector Length Agnostic 的思考
===

## real world example

- [Stencil codes on a vector length agnostic architecture](https://dl.acm.org/citation.cfm?id=3243192)

## CPP proposal for VLA

- [Vector Length Agnostic SIMD](http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2018/p1101r0.html)

## VLA hardware Spec

- ARM SVE
- https://llvm.org/devmtg/2016-11/Slides/Emerson-ScalableVectorizationinLLVMIR.pdf
- https://static.docs.arm.com/ddi0584/ae/DDI0584A_e_SVE_supp_armv8A.pdf
- RISCV Krste Asanovic 的 可變動 arch
- http://hwacha.org/papers/hwacha-mvp-prism2014.pdf
- https://people.eecs.berkeley.edu/~krste/papers/EECS-2015-265.pdf
- https://pdfs.semanticscholar.org/4bfe/e9693fe1f72bcce11316724ffac812a6ef37.pdf

## LLVM RFC

- LLVM RFC RISCV
- https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html
- LLVM RFC SVE
- http://lists.llvm.org/pipermail/llvm-dev/2018-July/124396.html
- LLVM Source SVE
- https://github.com/ARM-Software/LLVM-SVE

## SVE 現況

### 關鍵字

- SVE

## 內容

- (2018/06/05) [Supporting SIMD instruction sets with variable vector lengths](https://groups.google.com/forum/#!searchin/llvm-dev/Supporting$20SIMD$20instruction$20sets$20with$20variable$20vector$20lengths%7Csort:date/llvm-dev/TIEJ5-Y4jxU/DJjdaUB9AwAJ)
- 初始RFC
- Graham 這是 ARM 的人

- (2019/03/14) [Scalable Vector Types in IR - Next Steps](https://groups.google.com/forum/#!searchin/llvm-dev/SVE|sort:date/llvm-dev/tfeg5Xd_rBI/y3bAeeIoDAAJ)
- renato 開戰，「SVE到底還有沒有在做」
- Graham 回覆，「新的 IR type 先放一旁」
- (2019/05/01) [Update on scalable vector types and SVE upstreaming](https://groups.google.com/forum/#!searchin/llvm-dev/SVE|sort:date/llvm-dev/x5Yp_vEElmA/eO7ABmBDBAAJ)
- 最新的ARM官方進度說明
-