## RV32I Instruction ![image](https://hackmd.io/_uploads/H1EKKHZr1l.png) ### Opcode 0000011 : I-type(load) 0010011 : I-type 0010111 : U-type(auipc) 0011011 : I-type 0100011 : S-type(save) 0110011 : R-type 0110111 : U-type(lui) 1100011 : B-type 1100111 : I-type(jalr) 1101111 : J-type 1110011 : ecall ### 1. R-type |----Funct7----|---Rs2---|---Rs1---|--Funct3--|--Rd--|--opcode--| 31 25 24 20 19 15 14 12 11 7 6 0 #### opcode: **0110011** (64 bit-extension : 0111011) #### Funct: = Funct7 || Funct3 0000000 000 : add 0100000 000 : sub 0000000 001 : sll 0000000 010 : slt 0000000 011 : sltu 0000000 100 : xor 0000000 101 : srl 0100000 101 : sra 0000000 110 : or 0000000 111 : and ---- ### 2. I-type format1. |----Imm----|---Rs2---|---Rs1---|--Funct3--|--Rd--|--opcode--| 31 25 24 20 19 15 14 12 11 7 6 0 format2. |--Imm--|-0-|--Shamt--|---Rs1---|--Funct3--|--Rd--|--opcode--| 31 26 24 20 19 15 14 12 11 7 6 0 #### opcode: 1. **0000011** 2. **0010011** 3. **0011011** #### Funct3: ##### opcode: 0000011 all format1 000 : lb 001 : lh 010 : lw 011 : ld 100 : lbu 101 : lhu 111 : lwu ##### opcode: 0010011 000 : addi format1 001 : slli f2 010 : slti format1 011 : sltiu format1 100 : xori format1 101 : srli/srai f2 110 : ori format1 111 : andi format1 ##### opcode: 0011011 000 : addiw format1 001 : slliw f2 (Shamt:) 101 : srliw f2 101 : sraiw f2 ---- ### 3. S-type |----Imm----|---Rs2---|---Rs1---|--Funct3--|--Rd--|--opcode--| 31 25 24 20 19 15 14 12 11 7 6 0 #### opcode: **0100011** #### Funct3: 000 : sb 001 : sh 010 : sw 011 : sd ---- ### 4. B-type |-Imm1-|-imm3-|---Rs2---|---Rs1---|--Funct3--|-imm4-|-imm2-|--opcode--| 31 30 29 25 24 20 19 15 14 12 11 7 6 5 4 0 #### Imm = Imm1|Imm2|Imm3|Imm4 #### opcode: **1100011** #### Funct3 000 : beq 001 : bne 100 : blt 101 : bgt 110 : bltu 111 : bgtu --- ### 5. U-type |---------Imm---------|--Rd--|--opcode--| 31 12 11 7 6 0 #### opcode: **0110111**(lui, load upper immediate ) **0010111**(auipc, add upper immediate to pc) --- ### 6. J-type |---------Imm---------|--Rd--|--opcode--| 31 12 11 7 6 0 #### opcode: **1101111** ### B-extension Belonging to **'I-type'**, each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name. Some instructions are available in only one extension while others are available in several #### Zba(3 ins avalible in RV32): sh1add, sh2add, sh3add, #### Zbb(18 ins avalible in RV32): andn, orn, xnor, clz, ctz, cpop, max, maxu, min, minu, sext.b, sext.h, zext.h rol, ror, rori, orc.b, rev8 #### Zbc(3 ins avalible in RV32): clmul, clmulh, clmulr, #### Zbs(8 ins avalible in RV32): bclr, bclri, bext, bexti, binv, binvi, bset, bseti ### Ref ["B" Extension for Bit Manipulation, Version 1.0.0](https://github.com/riscv/riscv-isa-manual/blob/main/src/b-st-ext.adoc#zba) #### Mem_ReadEnable: Typese = L-Type