# [verilog](/OOks6GR3Rb-a27zveJAnWw)除三除頻器

先上code

module div3(
input clk,
output div3_clk
//output reg rising_clk=1'd0,falling_clk=1'd0
);

////rising edge part
reg [1:0]counter_rising=2'd0;
reg rising_clk=1'd0;

//counter

always@(posedge clk)
begin
	if (counter_rising==2'd2) counter_rising<=1'd0;
	else counter_rising<=counter_rising+1'd1;
end

//div
always@(posedge clk)
begin
	if (counter_rising==2'd2) rising_clk<=1'd1;
		else rising_clk<=1'd0;
end

////falling edge part
reg [1:0]counter_falling=2'd0;
reg falling_clk=1'd0;

//counter

always@(negedge clk)
begin
	if (counter_falling==2'd2) counter_falling<=1'd0;
	else counter_falling<=counter_falling+1'd1;
end

//div
always@(negedge clk)
begin
	if (counter_falling==2'd2) falling_clk<=1'd1;
		else falling_clk<=1'd0;
end

//combinational

assign div3_clk=(falling_clk|rising_clk);

endmodule

畫圖會更好理解 建議畫一下 一個正緣一個負緣計數器 0~2的計數器
當數到2的時候為1 其他為0 正負緣都是一樣

最後輸出再把他or起來
剛好可以湊一個0.5clk