# Implement controller of transducer in Verilog by FPGA (demo2)

 /* 
 
 Filename    : top_module.v
 Simulator   : Quartus II 20.1 ModelSim 2020.1
 scription   : 第二版Transducer控制電路
 Release     : Aug.30,2021

 */

module top_module (
	input clk,
	input reset,
	output reg ch1
	);

//===========================================
//parameter 
//===========================================

parameter start_n_ms=32'd3000, //一開始要延遲多久
clk_count=32'd150000000, //要幾個clk
//clk的週期要多少


//state parameter
idle_state=1'd0,
clk_state=1'd1,
stop_state=2'd2;


//===========================================
//reg
//===========================================

reg [31:0] count_nms;
reg [31:0] start_n_ms_reg=start_n_ms;
reg [31:0]nms_counts;
reg [31:0] clk_count_reg=clk_count; //用來存放clk state要數的的clk數量
reg [31:0] clk_count_cnt; //clk state的計數器
reg [1:0] state=idle_state , next_state;

//===========================================
//數nms所需的clk數 (clk為50Mhz)
//===========================================
always@(*)
begin
	nms_counts=start_n_ms_reg*50000;
end

//===========================================
//數nms的counter (clk為50Mhz)
//===========================================
always@(posedge clk)
 begin
 	if (reset || state!=1'd0) begin 
 	count_nms<=1'd0;
 	end
 		else if (count_nms == nms_counts-1'd1) begin
 		count_nms<=1'd0;
 		end
 			else begin
 			count_nms<=count_nms+1'd1;
 			end
 end


// //===========================================
// //輸出波型 (clk)
// //===========================================

always@(posedge clk)
begin
    if (reset || state!=1'd1) begin
        clk_count_cnt<=1'd0;
    end 
        else if (clk_count_cnt==clk_count_reg-1'd1) begin
            clk_count_cnt<=1'd0;
            end

            else begin
            clk_count_cnt<=clk_count_cnt+1'd1; 
            end
end

// //===========================================
// //fsm
// //===========================================

always@(posedge clk)
begin
    if (reset) state<=idle_state;
        else state<=next_state;
end

always@(*)
begin
    case (state)
    idle_state: if (count_nms == nms_counts-1'd1) next_state=clk_state;
        else next_state=state;
    clk_state: if (clk_count_cnt == clk_count_reg-1'd1) next_state=stop_state;
        else next_state=state;
    stop_state: next_state=state;
    default: next_state=state;
    endcase 
end

always@(*)
begin
    case (state)
    idle_state: ch1=1'd0;
    clk_state: ch1=clk;
    stop_state: ch1=1'd0;
    default: ch1=1'd0;
    endcase 
end

endmodule

tb

 /* 
 
 Filename    : top_module.v
 Simulator   : Quartus II 20.1 ModelSim 2020.1
 scription   : 第二版Transducer控制電路tb
 Release     : Aug.30,2021

 */

//================================================================
//設定timescale
//================================================================
`timescale 1ns/100ps

//================================================================
//設定testbench名
//================================================================
module top_module_test;


//================================================================
//input用reg output用wire
//================================================================
reg reset,clk;
wire  ch1;

//================================================================
//引用待測模組
//================================================================
top_module t1(.reset(reset),
            .clk(clk),
            .ch1(ch1));

//================================================================
//clk signal
//================================================================
initial #0 clk=1'b0;
always #10 clk =~clk;

//================================================================
//input
//================================================================
initial
begin: in_set_blk
    
    #0  reset=1'd1;
    #20 reset=1'd0;

end

//================================================================
//signals display
// //================================================================
initial
begin: display_set_blk
    integer i;
    for (i=0;i<80;i=i+1) begin
    #500000 $display (" time=",$time, " count_nms=%d clk_count_cnt=%d \n",t1.count_nms,t1.clk_count_cnt); //0.5ms取一次資料
        $display (" time=",$time, " state=%d next_state=%d \n",t1.state,t1.next_state);
        end
    #10 $stop;
    #10 $finish;
end
        
endmodule