---
# System prepended metadata

title: count clock

---

# count clock

```=v
module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss); 


//reg
reg [7:0] sec_cnt;
reg [7:0] min_cnt;
reg [7:0] hour_cnt;

//reg assign

always@(*)
begin
	ss=sec_cnt;
	mm=min_cnt;
	hh=hour_cnt;
end

//sec_cnt

////sec_cnt個位
always@(posedge clk)
begin
	if (reset) 
	sec_cnt[3:0]<=1'd0;
	
	else if (ena)
		begin
			if (sec_cnt[3:0]==4'd9)  
			sec_cnt[3:0]<=1'd0;
				
			else 
			sec_cnt[3:0]<=sec_cnt[3:0]+1'd1;
		
		end
end

////sec_cnt十位
always@(posedge clk)
begin
	if (reset) 
	sec_cnt[7:4]<=1'd0;
		else if (ena)
		begin
			if (sec_cnt[7:4]==3'd5 && sec_cnt[3:0]==4'd9)  
			sec_cnt[7:4]<=1'd0;
			
			else if(sec_cnt[3:0]==4'd9)
			sec_cnt[7:4]<=sec_cnt[7:4]+1'd1;
			
			else
			sec_cnt[7:4]<=sec_cnt[7:4];

		end
end

//min_cnt

//min_cnt 個位

always@(posedge clk)
begin
	if (reset) 
	min_cnt[3:0]<=1'd0;
	
	else if (ena)
		begin
			if (min_cnt[3:0]==4'd9 && sec_cnt[7:0]==8'b0101_1001)  
			min_cnt[3:0]<=1'd0;
				
			else if (sec_cnt[7:0]==8'b0101_1001)
			min_cnt[3:0]<=min_cnt[3:0]+1'd1;

			else
			min_cnt[3:0]<=min_cnt[3:0];

		end
end

//min_cnt 十位

always@(posedge clk)
begin
	if (reset) 
	min_cnt[7:4]<=1'd0;
	
	else if (ena)
		begin
			if (min_cnt[7:4]==3'd5 && sec_cnt[7:0]==8'b0101_1001 && min_cnt[3:0]==4'd9)  
			min_cnt[7:4]<=1'd0;
				
			else if (sec_cnt[7:0]==8'b0101_1001 && min_cnt[3:0]==4'd9)
			min_cnt[7:4]<=min_cnt[7:4]+1'd1;

			else
			min_cnt[7:4]<=min_cnt[7:4];

		end
end

//hour_cnt 

//hour_cnt 個位

always@(posedge clk)
begin
	if (reset) 
	hour_cnt[3:0]<=2'd2;
	
	else if (ena)
		begin
			if ((hour_cnt[3:0]==4'd9 && sec_cnt[7:0]==8'b0101_1001 && min_cnt[7:0]==8'b0101_1001) )  
			hour_cnt[3:0]<=1'd0;

			else if ((hour_cnt==8'h12 && sec_cnt[7:0]==8'b0101_1001 && min_cnt[7:0]==8'b0101_1001))
			hour_cnt[3:0]<=1'd1;
				
			else if (sec_cnt[7:0]==8'b0101_1001 && min_cnt[7:0]==8'b0101_1001)
			hour_cnt[3:0]<=hour_cnt[3:0]+1'd1;

			else
			hour_cnt[3:0]<=hour_cnt[3:0];

		end
end


//hour_cnt 十位

always@(posedge clk)
begin
	if (reset) 
	hour_cnt[7:4]<=1'd1;
	
	else if (ena)
		begin
			if (hour_cnt==8'b0001_0010 && sec_cnt[7:0]==8'b0101_1001 && min_cnt[7:0]==8'b0101_1001)  
			hour_cnt[7:4]<=1'd0;
				
			else if (hour_cnt[3:0]==4'd9 && sec_cnt[7:0]==8'b0101_1001 && min_cnt[7:0]==8'b0101_1001)
			hour_cnt[7:4]<=hour_cnt[7:4]+1'd1;

			else
			hour_cnt[7:4]<=hour_cnt[7:4];

		end
end

//pm

always@	(posedge clk)
begin
	if (reset) pm<=1'd0;
		else if (hh==8'h11 && mm==8'h59 && ss==8'h59) pm<=~pm;
			else pm<=pm;
end

endmodule 
```