/* 
 ===============================================================
 Filename    : spi_top_module.v
 Simulator   : Quartus II 20.1 ModelSim 2020.1
 scription   : spi controller
 Release     : Aug.20,2021
 ===============================================================
 */
 
module spi_top_module(
input clk,
input go,
input reset,
input [15:0] regdata,
output reg sdat,
output reg spc,
output reg scen,
output reg ordy
);


//initial



initial begin
sdat=1'bz;
spc=1'b1;
scen=1'b1;
ordy=1'b0;
end


//parameter


parameter 

idle_state=2'd0,
start_state=2'd1,
data_state=2'd2,
finish_state=2'd3;


//regs


reg [1:0]state,next_state;
reg [15:0] shift_regs_data_state;
reg [3:0] counter_data_state;



//fsm


always@(posedge clk)
begin
	if (reset) state<=idle_state;
		else state<=next_state;
end

always@(*)
begin
	case (state)
	idle_state: if (go) next_state=start_state;
						else next_state=state;
	start_state: next_state=data_state;
	data_state: if (counter_data_state==4'd15) next_state=finish_state;
						else next_state=state;
	finish_state: next_state=idle_state;
	endcase
end

always@(*)
begin
	case (state)
	idle_state:begin
	sdat=1'bz;
	spc=1'd1;
	scen=1'd1;
	ordy=1'd0;
	end
	
	start_state:begin
	sdat=1'bz; //shift reg
	spc=1'd1;
	scen=1'd0;
	ordy=1'd0;
	end
	
	data_state:begin
	sdat=shift_regs_data_state[15];
	spc=~clk;
	scen=1'd0;
	ordy=1'd0;
	end
	
	finish_state:begin
	sdat=1'bz;
	spc=~clk;
	scen=1'd1;
	ordy=1'd1;
	end
	
	endcase
end


/*
===============================================================
shift_reg_for_data_state
===============================================================
*/


always@(posedge clk)
begin
	case (state)
	
	start_state: shift_regs_data_state<=regdata;
	
	data_state: begin
	
	/*shift_regs_data_state[0]<=1'd0;
	shift_regs_data_state[1]<=shift_regs_data_state[0];
	shift_regs_data_state[2]<=shift_regs_data_state[1];
	shift_regs_data_state[3]<=shift_regs_data_state[2];
	shift_regs_data_state[4]<=shift_regs_data_state[3];
	shift_regs_data_state[5]<=shift_regs_data_state[4];
	shift_regs_data_state[6]<=shift_regs_data_state[5];
	shift_regs_data_state[7]<=shift_regs_data_state[6];
	shift_regs_data_state[8]<=shift_regs_data_state[7];
	shift_regs_data_state[9]<=shift_regs_data_state[8];
	shift_regs_data_state[10]<=shift_regs_data_state[9];
	shift_regs_data_state[11]<=shift_regs_data_state[10];
	shift_regs_data_state[12]<=shift_regs_data_state[11];
	shift_regs_data_state[13]<=shift_regs_data_state[12];
	shift_regs_data_state[14]<=shift_regs_data_state[13];
	shift_regs_data_state[15]<=shift_regs_data_state[14];*/
	
	shift_regs_data_state[15:0]<={shift_regs_data_state[14:0],1'd0};
	
	end
	
	default: shift_regs_data_state<=1'd0;
	
	endcase 
	
end

//////////////////////////////////////////////////
//counter_for_data_state
//////////////////////////////////////////////////

always@(posedge clk)
begin
	case (state)
	data_state: counter_data_state<=counter_data_state+1'd1;
	default :counter_data_state<=1'd0;
	endcase
	
end

endmodule