# [verilog] serial receiver

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output reg done
); 

	reg [3:0]state,nextstate;
	
	always@(posedge clk)
	begin
		if (reset) state<=1'd0;
			else state<=nextstate;
	end
	
	always@(*)
	begin
		case(state)
		4'd0: 
			if (in) nextstate<=4'd0;
			else nextstate<=4'd1;
		4'd1:
			nextstate<=4'd2;
		4'd2:
			nextstate<=4'd3;
		4'd3:
			nextstate<=4'd4;
		4'd4:
			nextstate<=4'd5;
		4'd5:
			nextstate<=4'd6;
		4'd6:
			nextstate<=4'd7;
		4'd7:
			nextstate<=4'd8;
		4'd8:
			nextstate<=4'd9;
		4'd9:
			if (in) nextstate<=4'd10;
			else nextstate<=4'd11;
		4'd10: 
			if (in) nextstate<=4'd0;
			else nextstate<=4'd1;
		4'd11:
			if (in) nextstate<=4'd0;
			else nextstate<=4'd11;
		default:nextstate<=4'd0;
		endcase
	end
	
	always@(*)
	begin
		case (state)
		4'd10: done<=1'd1;
		default: done<=1'd0; 
		endcase
	end
	
endmodule