# 系統晶片設計 SOC Design
- 課程時間：112 Autumn
- 授課教授：賴瑾老師
- 修課學生:交大機械所黃鉦淳同學

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## Personal Study
- Lab1 - Tool installation
> 介紹三種軟體(Vitis HLS/Vivado/MobaXterm)，將 C++ 語言經過下列方法燒錄至 OnlineFPGA ，並進行遠端驗證

[Study - Lab1](https://hackmd.io/@sgetCe01S4mRk6E7V5ju-Q/B1-IAeDk6)

- Lab2 - FIR using AXI Protocol to transmit/receive data
> 學習兩種端口(AXI Master/ AXI Stream)將資料從 PS (Processing System) 傳送至 PL (Programable Logic)完成FIR Filter

[Study - Lab2](https://hackmd.io/@sgetCe01S4mRk6E7V5ju-Q/HJ1nn2ZeT)

- Lab3 - FIR Design on hardware
> 用verilog設計一套符合端口(AXI Master/ AXI Stream)資料輸入/輸出的FIR系統

[Study - Lab3](https://hackmd.io/@sgetCe01S4mRk6E7V5ju-Q/H1on_IRda)

## Team Study
- Lab4 - FIR Design on hardware/software
> Caravel SOC系統分為硬體(Verilog Code - User Project)/韌體(C Code- firmware)，藉由此套系統模擬存放韌體機器碼(C Code)是在DFFRAM或是在BRAM儲存
- Lab4 - Basic Knowledge
[Study - Lab4](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/BknfcXy86)
- Lab4.0 - Caravel SOC Simulation
[Study - Lab4.0](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/SkC0vJ1UT)
- Lab4.1 - FIR software in Caravel SOC extermal BRAM
[Study - Lab4.1](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/HybFQWkIT)
- Lab4.2 - FIR hardware in Caravel SOC user project
[Study - Lab4.2](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/BJXPryyIp)
- Lab5 - Caravel SOC on FPGA
> 將整套Caravel SOC放到FPGA系統上進行驗證，並透過jupyter notebook進行燒錄機器碼(C Code)

[Study - Lab5](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/SylwG8srT)

- Lab6 - Workload optimized(FIR/Matirx Multiplication/Quick Sort/UART)
> 將FIR/矩陣乘法(matmul)/快速排序法(qsort)/UART放到Caravel SOC系統上進行模擬，更改機器碼/韌體執行順序使執行時間更短

[Study - Lab6](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/HJCbuEl8a)

- LabD - Replace BRAM with SDRAM Controller & SDRAM
> 由於BRAM需要10T(period)的存取時間，替換成SDRAM最多僅需9T。但因為SDRAM的設計，750T需要刷新(Refresh)一次

[Study - LabD](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/rJwfPX-w6)

## 補充
- A1 - FIFO(First In First Out)
[Study - FIFO](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/HkPUnI786)

- A2 - SDRAM(Synchronous Dynamic Random-access Memory)
[Study - SDRAM](https://hackmd.io/@861r6vBbQbu3FLGNe3SkyQ/Bk4DlHtP6)

## GitHub - Project
- [GitHub - Lab3](https://github.com/pocper/112_SOC_Lab/tree/main/Lab3)
- [GitHub - Lab4](https://github.com/pocper/112_SOC_Lab/tree/main/Lab4)
- [GitHub - Lab6](https://github.com/pocper/112_SOC_Lab/tree/main/Lab4)
- [GitHub - Final](https://github.com/pocper/112_SOC_final_project)

## 附錄
:::info
> 寫出爛Code才知道怎麼改進
:::

<center>
<video src="https://img2.doubanio.com/view/richtext/raw/public/p33472221.mp4" control autoplay loop>
</video>
</center>

<center>謝謝這學期辛苦的SOC Design助教!</center>