---
tags: 計算機組織, 資工系必修
---
# Exam 1
109暑 計算機組織 蔡文錦
#### Q1. MIPS have three instruction formats: R, I, and J formats. Please choose the statements which correctly map the instructions and the corresponding instruction formats.
單選或多選：
a. jr is J-format
b. lw is I-format
c. bne is J-format
d. jal is J-format
e. slt is R-format
f. sll is R-format
**Ans: b. d. e. f.**
a. jr is R-format
c. bne is I-format
#### Q2. Suppose a program runs in 100 seconds on a machine, with floating-point (FP) operations responsible for 60 seconds of this time. Which of following statements are correct?
單選或多選：
a. If we want this program to run 2 times faster, we have to improve the FP operations 6 times faster.
b. If we can only improve the FP operations 3 times faster, the FP operations should account for 75 seconds (with old FP) so that this program can run two times faster.
**Ans: a. b.**
a. 100/2 == 60/6 + 40
b. 100/2 == 75/3 + 25
#### Q3. The C code for factorial is as follows and the corresponding MIPS codes are on the right side. Assume that the code sequence was called by 'jal fact' in the main program and where the content of \$a0 is 4 before the jal is called, which of following statements are correct?
```c
int fact (int n)
{
if (n < 1) return 1;
else return n * fact(n - 1);
}
```
單選或多選：
a. The total number of MIPS instructions executed before returning back to the main program is 56. (not include the “jal fact” in main program).
b. Right after the instruction “mul \$v0, \$a0, \$v0” has completed the 3rd execution, the content of \$v0 is 6.
c. The instruction “beq \$t0, \$zero, L1” will be executed for 4 times.
**Ans: a. b.**
a. $7 \times 4 + 5 + 3 + 5 \times 4 = 56$
b. That is Factorial. Three times will be $3 \times 2 \times 1 = 6$
c. 5 times (4 times branch, 1 times no branch)
#### Q4. Given an ALU where the figures below only show its most-significant-bit ALU (called ALU31) and other bit (b0~b30) ALU (i.e., ALU0~ALU30). Assume the 32 ALUs are connected correctly, which of following statements are correct?
| ALU31 | ALU0 ~ ALU30 |
|:------------------------------------:|:------------------------------------:|
|  |  |
單選：
a. To support slt instruction, the adder output of ALU31 must be connected to the input ' less' of all ALUs (i.e., ALU0~31)
b. The control signals for sub instruction is Aivert =0, Binvert = 1, Operation = 10b (b: binary)
c. Assume the circuits for slt instruction has been correctly connected, the control signals for slt are Ainvert=0, Binvert=0, Operation=11b
d. To support instruction NAND for this ALU, we can set control signals as Aivert = 1, Binvert = 1, Operation = 00b
**Ans: b.**
a. must be connected to to the input ' less' of ALU0 and others connect 0.
c. Ainvert=0, Binvert=1, Operation=11b
d. Aivert = 1, Binvert = 1, Operation = 01b
#### Q5. Given the sequence of MIPS machine codes below. Which of following statements are corrects?
| address | | |
| ---------- | --- | ---------------------------------------------- |
| 8000 0002h | L1: | 0000 0000 0000 0000 0100 0000 0010 0000 |
| | L2: | 0001 0010 0100 0000 0000 0000 0000 0011 |
| | L3: | 0000 0001 0001 0001 0100 0000 0010 0000 |
| | L4: | 0010 0010 0101 0010 1111 1111 1111 1110 |
| | L5: | 0000 1000 0000 0000 0000 0000 0000 1001 |
| 8000 0034h | L6: | 0000 0000 0000 1000 0011 0000 1000 0000 |
| | add | sll | slt | addi | lw | sw | beq | bne | j | | | \$t0 | \$s0 | \$v0 |
| ---- | --- | --- | --- | ---- | --- | --- | --- | --- | --- | --- | ----- | ---- | ---- | ---- |
| op | 0 | 0 | 0 | 8 | 35 | 45 | 4 | 5 | 2 | | Reg\# | 8 | 16 | 6 |
| func | 32 | 0 | 24 | | | | | | | | | | | |
Note: all the numbers are decimal.
單選：
a. Assume \$s1 and \$s2 contain 3 and 8, respectively, before the code runs. The \$v0 will contain 24 after the execution of the code sequence.
b. The instruction at L2 is beq \$s2, \$zero, L5
c. The instruction at L4 is addi \$s2, \$s2, -1
d. The instruction at L6 is sll \$v0, \$t0, 2
e. The instruction at L5 is j L1
f. The instruction at L3 is add \$t0, \$s1, \$t0
**Ans: d.**
a. The \$v0 will contain 48.
b. beq \$s2, \$zero, L6
c. addi \$s2, \$s2, -2
e. j L2
f. add \$t0, \$t0, \$s1
The code in MIPS:
```c
L1: add $t0, $zero, $zero
L2: beq $s2, $zero, L6
L3: add $t0, $t0, $s1
L4: addi $s2, $s2, -2
L5: j L2
L6: sll $v0, $t0, 2
```
#### Q6. The table below shows the number of instructions executed and the average CPI for executing applications 1 and 2 on three different machines. Machine A has a clock rate of 2 GHz, machine B, 2 GHz, and machine C, 4 GHz. Which of following statements are correct?
<table>
<tr>
<td> </td>
<td colspan="2">Machine A (2GHz)</td>
<td colspan="2">Machine B (2GHz)</td>
<td colspan="2">Machine C (4GHz)</td>
</tr>
<tr>
<td> </td>
<td>Instructions</td>
<td>Avg CPI</td>
<td>Instructions</td>
<td>Avg CPI</td>
<td>Instructions</td>
<td>Avg CPI</td>
</tr>
<tr>
<td>App 1</td>
<td>4.0E+9</td>
<td>1</td>
<td>2.0E+10</td>
<td>5</td>
<td>1.0E+11</td>
<td>1</td>
</tr>
<tr>
<td>App 2</td>
<td>4.0E+11</td>
<td>5</td>
<td>2.0E+10</td>
<td>6</td>
<td>2.0E+11</td>
<td>2</td>
</tr>
</table>
單選或多選：
a. If we consider App1 and App2 are equally important, machine A is the fastest.
b. If we consider App1 and App2 are equally important and use machine A as the reference, then machine B's geometric mean is less than 1.
c. If both App1 and Appl2 run once a week, machine A is the fastest.
d. If App1 must run ten times as often as App2 in a week, machine A is the fastest.
**Ans: a. b.**
a. b. If use machine A as the reference, then machine B's geometric mean is $0.\bar{6}$ and machine C's geometric mean is $0.8$
| | A | B | C |
| ----- | -------- |:-------:|:-------:|
| App 1 | 2 sec | 50 sec | 25 sec |
| App 2 | 1000 sec | 60 sec | 100 sec |
c. A: 1002 sec, B: 110 sec, C: 125 sec
d. A: 1020 sec, B: 560 sec, C: 350 sec
#### Q7. Consider a MIPS program. Assume the PC is at 0x00000060, which of following addresses can be reached by using a single jump instruction?
單選：
a. 0x08000060
b. 0xFFF00000
c. 0x0000005F
d. 0xFFFFFFF0
**Ans: a.**
b. d. first 4-bit shoud be same with PC
c. last 2-bit shoud be 00
#### Q8. For the loops written in MIPS assembly, assume that the $s1, $s2, $t1 are initialized to 0xffff, 0x0, and 0x5, respectively. Which of following statements are correct for the execution of this code sequence?
```c
Loop: addi $t2, $zero, 0xfff0
srl $s1, $s1, 1
Loop2: addi $s2, $s2, 1
addi $t2, $t2, 2
bne $t2, $zero, Loop2
addi $t1, $t1, -1
bne $t1, $zero, Loop
Done:
```
單選：
a. \$s2 will contain value 8 after the execution.
b. \$s1 will contain value 0xffff after the execution.
c. The number of instructions that will be executed is 140.
**Ans: c.**
a. \$s2 will contain value 40 after the execution.
b. \$s1 will contain value 0x07ff after the execution.
c. $(2+8\times3+2)\times5=140$
#### Q9. Which of the following 32-bit data have identical binary representation in memory no matter little endian or big endian is used
單選：
a. 0xABCDCDAB
b. 0xABCDABCD
c. 0xABAB
d. 0xABCDDCBA
**Ans: a.**
#### Q10. Given the two code sequences below, where assume that $t0 is initialized to 0 and $s1 is initialized to 1000 before the code running. Which of following statements are correct?
Code sequence 1
```c
lui $t0, 0x1234
ori $t0, $t0, 0x5678
```
Code sequence 2
```c
ori $t0, $t0, 0x5678
lui $t0, 0x1234
```
單選或多選：
a. If we add instruction sw \$t0, 0(\$s1) after the code sequence 1, the content at memory address 1000 will be 0x12 after the execution of this new code sequence.
b. After the execution of code sequence 1, the \$t0 contains 0x12345678
c. If we add instruction sb \$t0, 0(\$s1) after the code sequence 1, the content at memory address 1000 will be 0x78 after the execution of this new code sequence
d. After the execution of code sequence 2, the \$t0 contains 0x12345678
**Ans: a. b. c.**
d. \$t0 contains 0x12340000
#### Q11. Assume i, j, f, and g correspond to $s1, $s2, $s3 and $s4, respectively. Please choose the correct MIPS instructions for the MIPS program corresponding to the C code below.
```c
if ( i > j ) f = g;
else f = 0x1234ABCD;
```
單選或多選：
a. A: slt \$t0, \$s2, \$s1 B: beq \$t0, \$zero, L1
b. C: add \$s3, \$s4, \$zero D: bne \$t0, \$zero, L2
c. C: add \$s3, \$s4, \$zero D: j L2
d. E: add \$s3, \$zero, 0x1234ABCD
e. A: slt \$t0, \$s2, \$s1 B: bne \$t0, \$zero, L1
**Ans: a. c.**
d.
```c
lui $s3, 0x1234
ori $s3, $s3, 0xABCD
```
#### Q12. MIPS instructions follow the four design principles below. Please choose the statements which correctly map the design examples and the corresponding design principles.
A. Simplicity favors regularity
B. smaller is faster
C. Make common case faster
D. Good design demands a good compromise
單選或多選：
a. Use three operands in all arithmetic instructions ➜ follow principle A
b. Use immediate constant as one of the operands in arithmetic instructions ➜ follow principle B
c. Use three instruction formats to keep all instructions the same lengths ➜ follow principle D
d. Use registers as operands in arithmetic and logic instructions ➜ follow principle C
**Ans: a. c.**
b. follow principle C
d. follow principle B
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