# Implement a 16-bits adder in Verilog HDL by using four 4 bits full adders.
第14組
A1115530 劉柏均
A1115531 錢昱名

## introduce

This is a 16-bits adder by using 4 bits full adders.

## implement

We wrote 1 bit full adder as a function at first.

It is very obviously that there is 3 input and 2 out put.

a+b+cin, assign low bit to sum, and high bit to cout.


In order to apply the request, we have to implement 4bit adder.
Due to readability, we use bus to input and output the signal.

let fa = fulladder
output of fa0 is c0, and input to the input of fa1 and so on.


The different of 16bit adder between 4bit adder and Fulladder is
using bus input to the 4bit adder.


Wonderful, simulate the signal.

Let we check the reslut.
53394+45922 = 33780 and overflow.
correct.

2475+34274 = 36749 correct
24883+12669 = 37552 correct

# Discussion
We think useing Verilog HDL to simulate a electrical circuit is very convenient.
Useing Verilog HDL is familiar to us.