---
# System prepended metadata

title: HDL-HW20221209
tags: [hdl, hw, thu]

---

###### tags: `hdl` `hw` `thu`
{%hackmd theme-dark %}
# HDL-HW20221209

## AND GATE
```verilog=
module my_and(output out, input a, b);     
        supply1 pwr; supply0 gnd;                        
    
        // get xnor 
        wire xnor_out;                                   
        pmos (xnor_out, pwr, b);                         
    
        wire t1;
        nmos (xnor_out, t1, b);                          
        nmos (t1, gnd, a);  
        pmos (xnor_out, pwr, a);                                                                    
        // not the xnor                                  
        not G3 (out, xnor_out);                          
endmodule     
```
![](https://i.imgur.com/s88uNmn.png)

## OR GATE
```verilog=
module my_or (output out, input a, b);                     
        supply1 pwr; supply0 gnd;                          
        
        wire t1, t2;
        pmos (t1, pwr, a);
        pmos (t2, t1, b);
        nmos (t2, gnd, b);
        nmos (t2, gnd, a);                                 
                                                           
        pmos (out, pwr, t2);                               
        nmos (out, gnd, t2);                               
endmodule
```
![](https://i.imgur.com/RFVPbw8.png)

## XOR GATE
```verilog=
module my_not (output out, input a);
        supply1 pwr; supply0 gnd;

        pmos (out, pwr, a);
        nmos (out, gnd, a);
endmodule


module my_xor(output out, input a, b);
        supply1 pwr; supply0 gnd;

        // get not A, B
        wire not_a, not_b;
        my_not G1 (not_a, a);
        my_not G2 (not_b, b);

        // implement A xor B: PMOS
        wire t1, t2;
        pmos (t1, pwr, a);
        pmos (out, t1, not_b);
        pmos (t2, pwr, not_a);
        pmos (out, t2, b);


        // implement A xor B: NMOS
        wire t3, t4;
        nmos (out, t3, a);
        nmos (t3, gnd, b);
        nmos (out, t4, not_a);
        nmos (t4, gnd, not_b);
endmodule
```
![](https://i.imgur.com/Rk1ijNi.png)

## Full Adder
```verilog=
module fullAdder (output sum, c_out, input a, b, c_in);    
        wire t1, t2, t3;                                   
        my_xor  G1 (t1, a, b),
                G2 (sum, t1, c_in);                        
        my_and  G3 (t2, a, b),
                G4 (t3, t1, c_in);
        my_or   G5 (c_out, t2, t3);
endmodule
```
![](https://i.imgur.com/LTi7fSa.png)

