---
# System prepended metadata

title: CO-HW
tags: [computer organization, hw, thu]

---

###### tags: `computer organization` `hw` `thu`

{%hackmd theme-dark %}

# CO-HW


## 1. Please draw the pipeline diagram for the following two cases.
![](https://i.imgur.com/TemAGQu.png)
![](https://i.imgur.com/yCnWw0F.png)

### Ans:
#### 1. 
| 指令 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
| -------- | -------- | -------- |-|-|-|-|-|-|-|-|-|-|-|
| `lw $t1, 0($t0)`     | IF | ID | EX | MEM | WB |
| `lw $t2, 4($t0)`| |  IF | ID | EX | MEM | WB |
| `STALL` | | | X | X | X | X | X | 
| `add $t3, $t1, $t2` | | | | IF | ID | EX | MEM | WB |
| `sw $t3, 12($t0)` | | ||  | IF | ID | EX | MEM | WB |
| `lw $t4, 8($t0)` | | | | | | IF | ID | EX | MEM | WB |
| `STALL` | || | | |  | X | X | X | X | X |
| `add $t5, $t1, $t4` |  | | | | | | | IF | ID | EX | MEM | WB |
| `sw $t5, 16($t0)` | | | | | | | | | IF | ID | EX | MEM | WB |

#### 2. 
| 指令 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 
| -------- | -------- | -------- |-|-|-|-|-|-|-|-|-|
| `lw $t1, 0($t0)`     | IF | ID | EX | MEM | WB |
| `lw $t2, 4($t0)`| |  IF | ID | EX | MEM | WB |
| `lw $t4, 8($t0)` | | | IF | ID | EX | MEM | WB |
| `add $t3, $t1, $t2` | | | | IF | ID | EX | MEM | WB |
| `sw $t3, 12($t0)` | | ||  | IF | ID | EX | MEM | WB |
| `add $t5, $t1, $t4` |  | | | | | IF | ID | EX | MEM | WB |
| `sw $t5, 16($t0)` | | | | | | | IF | ID | EX | MEM | WB |

## 2. Optimization of Delay Branch
### Please use the following example to demonstrate the results after applying the technologies of Delay Branch and Optimization of Delay Branch, respectively.
|Address	|NormalBranch| |
|-|-|-|
|0100 |	Load	|A, X|
|0104|	Add	|A, 1|
|0108|	Jump	|0114|
|010C|	Add	|A, B|
|0110|	Sub	|C, B|
|0114|	Store|	A, Z|
|0118|	Load|	A, Y|
### Note: X, Y and Z is memory addresses, A, B, and C are registers, pipeline is I-E-D three stages, compiler will insert noop for pipeline stall

#### a. Draw the pipeline diagram for delay branch with inserting noop.

| 指令 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| -------- | -------- | -------- |-|-|-|-|-|-|-|-|
| `Load A, X`     | I     | E | D |
| `Add A, 1`| | I | | E | D|
| `Jump 0114` | | |  I| E | D|
| `NOOP` | | | | X | X | X |
| `Store A, Z` | | |  | | I | E | D
| `Load A, Y` | | | | | | I | E | D

#### b. Draw the pipeline diagram by using optimization of delay branch.

| 指令 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| -------- | -------- | -------- |-|-|-|-|-|-|-|-|
| `Load A, X`     | I     | E | D |
| `Jump 0114` | | I| E | D|
| `Add A, 1`| | | I | E | D|
| `Store A, Z` | | |  | I | E | D
| `Load A, Y` | | | | | I | E | D
