###### tags: `hdl` `test` `thu`
# HDL-TEST20221230
## EX01
### 15 ns:
- $A \rightarrow 0$
- $B \rightarrow 0$
### 25 ns:
- $C \rightarrow 0$
## EX02
### Module
```verilog=
module counter (output reg [2:0] cnt, input clk, clear);
always @ (posedge clk) begin
if (!clear)
cnt <= 0;
else
case (cnt)
0: cnt <= 1;
1: cnt <= 3;
3: cnt <= 7;
7: cnt <= 6;
6: cnt <= 4;
4: cnt <= 0;
endcase
end
endmodule
```
### Testbench
```verilog=
module test1_tb;
wire [2:0] cnt;
reg clk, clear;
counter circuit (cnt, clk, clear);
// output
initial begin
clk = 0; clear = 0;
#10 clear = 1;
#80 $finish;
end
always #5 clk = ~clk;
initial begin
$display ("\t\tTIME\tclear\t|\tcnt");
$display ("\t\t------------------------------------------------------------");
$monitor ("%t\t%b\t|\t%d", $time, clear, cnt);
end
endmodule
```

## EX03
### Task + Testbench
```verilog=
module test1_tb;
reg [9:0] sum;
reg [4:0] num;
// for task
reg [9:0] tmp;
reg [4:0] counter;
// output
initial begin
num = 12;
factorSum (sum, num);
#80 $finish;
end
initial begin
$display ("\t\tTIME\tnum\t|\tsum");
$display ("\t\t------------------------------------------------------------");
$monitor ("%t\t%d\t|\t%d", $time, num, sum);
end
task factorSum (output [9:0] sum, input [4:0] num); begin
tmp = 0; counter = 1;
if (num != 0) begin
while (counter <= num) begin
if (num % counter == 0)
tmp += counter;
counter++;
end
end
sum = tmp;
end endtask
endmodule
```

#### $28 = 1 + 2 + 3 + 4 + 6 + 12$
## EX04
### Function + Testbench
```verilog=
module test1_tb;
reg [8:0] sum;
reg [3:0] num;
// output
initial begin
$display ("\t\tTIME\tnum\t|\tsum");
$display ("\t\t------------------------------------------------------------");
$monitor ("%t\t%d\t|\t%d", $time, num, sum);
num = 0;
while (num < 12) begin
#1 num += 1;
sum = Fib(num);
end
#20 $finish;
end
initial begin
end
function automatic integer Fib (input [3:0] terms); begin
if (terms == 0 || terms == 1)
Fib = 1;
else
Fib = Fib (terms - 1) + Fib (terms - 2);
end endfunction
endmodule
```
