---
# System prepended metadata

title: HDL-HW20221028
tags: [hdl, hw, thu]

---

###### tags: `hdl` `hw` `thu`
{%hackmd theme-dark %}

# HDL-HW20221028

## EX01
### Problem
![](https://i.imgur.com/quOIo6A.png)
### CODE
```verilog=
`define Y2RDELAY 3
`define R2GDELAY 2

module sig_control (output [1:0] hwy, cntry, input X, clock, clear);
	// variables
	reg [1:0] hwy, cntry;
	parameter 	RED = 2'd0,
       			YELLOW = 2'd1,
			GREEN = 2'd2;
					// country	highway	
	parameter	S0 = 3'd0, 	// RED		GREEN
			S1 = 3'd1,	// RED		YELLOW
			S2 = 3'd2,	// RED		RED
			S3 = 3'd3,	// GREEN	RED
			S4 = 3'd4;	// YELLOW	RED
	
	// internal
	reg [2:0] state, next_state;

	// change state to next_state upon posedge
	always @ (posedge clock)
		if (clear)
			state <= S0;
		else
			state <= next_state;

	
	// compute signal based on state
	always @ (state) begin
		hwy = GREEN;
		cntry = RED;
		if (state == S1)
			hwy = YELLOW;
		else if (state == S2)
			hwy = RED;
		else if (state == S3) begin
			hwy = RED;
			cntry = GREEN;
		end	
		else if (state == S4) begin
			hwy = RED;
			cntry = YELLOW;
		end
	end

	// compute next_state based on signal x
	always @ (state or X) begin
		if (state == S0)
			if (X) 	next_state = S1;
			else	next_state = S0;
		else if (state == S1) begin
			repeat (`Y2RDELAY) @ (posedge clock);
			next_state = S2;
		end
		else if (state == S2) begin
			repeat (`R2GDELAY) @ (posedge clock);
			next_state = S3;
		end
		else if (state == S3) 
			if (X) 	next_state = S3;
			else	next_state = S4;
		else if (state == S4) begin
			repeat (`Y2RDELAY) @ (posedge clock);
			next_state = S0;
		end
		else
			next_state = S0;
	end
endmodule
```
```verilog=
module test1_tb;

	wire [1:0] hwy, cntry;
	reg X, clock, clear;
	
	sig_control cmp1 (hwy, cntry, X, clock, clear);

	// setup data
	initial begin
		// generate clock
		clock = 1'b0;
		forever #5 clock = ~clock;
	end

	initial begin
		// control clear signal
		clear = 1'b1;
		repeat (5) @ (negedge clock);
		clear = 1'b0;
	end

	initial begin
		// input simulation data
		X = 1'b0;
		repeat (20) @ (negedge clock); X = 1'b1;
		repeat (10) @ (negedge clock); X = 1'b0;

		repeat (20) @ (negedge clock); X = 1'b1;
		repeat (10) @ (negedge clock); X = 1'b0;

		repeat (20) @ (negedge clock); X = 1'b1;
		repeat (10) @ (negedge clock); X = 1'b0;

		repeat (10) @ (negedge clock); $finish;
	end

	// output
	initial begin
		$display ("\t\tTIME\tX\t|\tHWY\tCNTRY");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%b\t|\t%2b\t%2b\n", $time, X, hwy, cntry);
	end
endmodule
```
### OUTPUT
```
iverilog test1.v test1_tb.v
vvp a.out
		TIME	X	|	HWY	CNTRY
		---------------------------------------
                   0	0	|	xx	xx

                   5	0	|	10	00

                 200	1	|	10	00

                 205	1	|	01	00

                 235	1	|	00	00

                 265	1	|	00	10

                 300	0	|	00	10

                 305	0	|	00	01

                 335	0	|	10	00

                 500	1	|	10	00

                 505	1	|	01	00

                 535	1	|	00	00

                 565	1	|	00	10

                 600	0	|	00	10

                 605	0	|	00	01

                 635	0	|	10	00

                 800	1	|	10	00

                 805	1	|	01	00

                 835	1	|	00	00

                 865	1	|	00	10

                 900	0	|	00	10

                 905	0	|	00	01

                 935	0	|	10	00
```

## EX02
### Problem
![](https://i.imgur.com/7NznEK3.png)

### CODE
```verilog
module alu_4bit (output [4:0] ans, input [2:0] sel, input [3:0] A, B);
	reg [4:0] ans;
	always @ (sel, A, B) begin
		case (sel)
			3'd0: ans <= A;
			3'd1: ans <= A+B;
			3'd2: ans <= A-B;
			3'd3: ans <= A/B;
			3'd4: ans <= A%B;
			3'd5: ans <= A<<1;
			3'd6: ans <= A>>1;
			3'd7: ans <= (A>B);
		endcase
	end
endmodule
```

```verilog
module test1_tb;
	wire [4:0] ans;
	reg [2:0] sel; reg [3:0] A, B;
	
	alu_4bit cmp1 (ans, sel, A, B);

	// setup data
	initial begin
			sel = 0; A = 3; B = 5;
		#5 	sel = 1; A = 4; B = 7;
		#5 	sel = 2; A = 4; B = 7;
		#5 	sel = 3; A = 8; B = 2;
		#5 	sel = 4; A = 11; B = 5;
		#5 	sel = 5; A = 4; B = 7;
		#5 	sel = 6; A = 4; B = 7;
		#5 	sel = 7; A = 4; B = 7;
		$finish;
	end

	// output
	initial begin
		$display ("\t\tTIME\tSel\tA\tB\t|\tANS");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%d\t%2d\t%2d\t|\t%2d\n", $time, sel, A, B, ans);
	end
endmodule
```

### OUTPUT
![](https://i.imgur.com/ExCifGK.png)

