---
# System prepended metadata

title: HDL-MIDTERM
tags: [test, hdl, thu]

---

###### tags: `hdl` `test` `thu`
{%hackmd theme-dark %}
# HDL-MIDTERM

## EX01
```verilog!
module test1_tb;
	reg [4:0] A, B;
	reg [3:0] C;
	reg [4:0] A1, B1;
	reg [3:0] C1;
	
	//blocking cmp1 (A, B, C);
	//nonblocking cmp2 (A1, B1, C1);


	// setup data
	initial begin
		A = 16; B = 25; C = 12;
		A1 = 16; B1 = 25; C1 = 12;

		#5 A = B; B = C; C = A;

		#10 A1<=B1; B1<= C1; C1<= A1;




		#15 $finish;
	end

	// output
	initial begin
		$display ("\t\tTIME\tA\tB\tC\t|\tA1\tB1\tC1");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%d\t%d\t%d\t|\t%d\t%d\t%d\n", $time, A, B, C, A1, B1, C1);
	end
endmodule
```
![](https://i.imgur.com/oxIsmbP.png)


## EX02
### a. Gate level
![](https://i.imgur.com/KYwdU1i.jpg)
![](https://i.imgur.com/zgN38vk.png)


### b. Behavioral modeling
![](https://i.imgur.com/ZfmEjUV.jpg)
![](https://i.imgur.com/jRX4uyN.png)

## EX03
### a. Dataflow modeling
![](https://i.imgur.com/NpyQjis.png)
![](https://i.imgur.com/UjckyvR.png)


### b. Behavioral modeling
![](https://i.imgur.com/9mouXUT.png)
![](https://i.imgur.com/JbRKHj1.png)


## EX04
### a. Dataflow
![](https://i.imgur.com/AizbQGM.jpg)
![](https://i.imgur.com/IvAAhRV.png)

### b. Behavioral modeling
![](https://i.imgur.com/TPcrfjY.png)
![](https://i.imgur.com/LVslsvo.png)


