###### tags: `hdl` `test` `thu`

# HDL-FINAL20230113

## EX01

$$i = 0, j = -1, a = 14, b = 16$$

## EX02
### CODE

module test1_tb;
	reg [31:0] num;
	reg [4:0] count;

	// setup
	initial begin
		num = 32'b1101_0101_1101_0101_1101_0101_1101_0101;
		count_occurence_110 (count, num);
		#10 $finish;
	end
	initial begin
		$display ("\t\tTIME\tnum\t|\tcount");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%b\t|\t%d", $time, num, count);
	end

	// task
	task count_occurence_110 (output [4:0] count, input [31:0] num); begin
		count = 0;
		while (num > 0) begin
			if (num[0] == 1 && num[1] == 1 && num[2] == 0) begin
				count++;
				num = num / 8;
			end
			else
				num = num / 2;
		end
	end endtask
endmodule

### RESULT

## EX03
### CODE

module pmos_nmos (output Q, nQ, input D);
	// var
	wire nD;
	NOT_pn circuit1 (nD, D);
	wire a1, a2;

	// wiring
	supply1 pwr; supply0 gnd;
	pmos (a1, pwr, Q);
	pmos (a2, pwr, nQ);

	pmos (nQ, a1, D);
	pmos (Q, a2, nD);

	nmos (nQ, gnd, D);
	nmos (nQ, gnd, Q);
	nmos (Q, gnd, nQ);
	nmos (Q, gnd, nD);
endmodule


module NOT_pn (output nD, input D);
	supply1 pwr; supply0 gnd;
	pmos (nD, pwr, D);
	nmos (nD, gnd, D);
endmodule

module test1_tb;
	reg D;
	wire Q, nQ;

	pmos_nmos circuit (Q, nQ, D);
	
	// setup
	initial begin
		D = 0;
		#40 $finish;
	end
	always #5 D = ~D;
	initial begin
		$display ("\t\tTIME\tD\t|\tQ\tnQ");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%b\t|\t%b\t%b", $time, D, Q, nQ);
	end

endmodule

### RESULT

## EX04

### CODE

module countQ1 (clk, Ld, Enable, S6, Q);
	input clk, Ld, Enable;
	output reg S6;
	output reg [7:0] Q;

	// variable
	reg [2:0] status, state;

	always @ (posedge clk) begin
		if (Ld) begin
			status = 0;
			S6 = 0;
			Q = 8'b10000000;
		end
	end

	always @ (posedge Enable) begin
		status ++;
		case (status)
			0: Q = 8'b10000000;
			1: Q = 8'b01000000;
			2: Q = 8'b00100000;
			3: Q = 8'b00010000;
			4: Q = 8'b00001000;
			5: Q = 8'b00000100;
			6: Q = 8'b00000010;
			7: Q = 8'b00000001;
		endcase
		if (status == 5) 
			S6 = 1;
		else
			S6 = 0;
	end

endmodule

module test1_tb;
	reg clk, Ld, Enable;
	wire S6; wire [7:0] Q;

	countQ1 circuit (clk, Ld, Enable, S6, Q);
	
	// setup
	initial begin
		Enable = 0;
		clk = 0;
		Ld = 1;
		#2 Ld = 0;

		#30 Ld = 1;
		#31 Ld = 0;
		
		#20 $finish;
	end

	always #1 clk = ~clk;
	always #2 Enable = ~Enable;

	initial begin
		$display ("\t\tTIME\tLd\tEnable\t|\tS6\tQ");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%b\t%b\t|\t%b\t%b", $time, Ld, Enable, S6, Q);
	end

endmodule

### RESULT

## EX05 (失敗)
### CODE

module coin (output reg orange, output reg [15:0] sum, input N, D, Q, rst, clk);
	always @ (rst) begin
		if (rst) begin
			orange = 0;
			sum = 0;
		end
	end

	always @ (posedge clk) begin
		if (Q) sum += 25;
		if (D) sum += 10;
		if (N) sum += 5;
		if (sum > 30) begin
			orange = 1;
			sum = 0;
		end
	end

endmodule

module test1_tb;
	reg N, D, Q, rst, clk;
	wire orange;
	wire [15:0] sum;

	coin circuit (orange, sum, N, D, Q, rst, clk);
	
	// setup
	initial begin
		N = 0; D = 0; Q = 0; rst = 1; clk = 0;
		#1 rst = 0;

		
		#20 $finish;
	end

	always #2 clk = ~clk;
	always #3 begin
		N = $random;
		D = $random;
		Q = $random;
		N = $random;
	end

	initial begin
		$display ("\t\tTIME\tN\tD\tQ\trst\t|\torange\tsum");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%b\t%b\t%b\t%b\t|\t%b", $time, N, D, Q, rst, orange, sum);
	end

endmodule

### RESULT