---
# System prepended metadata

title: HDL-TEST1
tags: [test, hdl, thu]

---

###### tags: `hdl` `test` `thu`
{%hackmd theme-dark %}
# HDL-TEST1

## EX01
### a. Implement it with gate level modeling.
``` verilog
module circuit (output F1, F2, input A, B, C, D);
	wire T1, T2, T3, T4;
	wire NOT_B, NOT_A, NOT_D;

	// setup
	not S1 (NOT_B, B),
		S2 (NOT_A, A),
		S3 (NOT_D, D);

	and 	G1 (T1, NOT_B, C),
			G2 (T2, NOT_A, B);
	or  	G3 (T3, A, T1),
			G4 (T4, T2, D);
	xor 	G5 (F2, T2, NOT_D);
	nand	G6 (F1, T3, T4);
endmodule
```


### b. Simulate it and construct its truth table based on the simulation result.
```verilog!
module test1_tb;
	reg A, B, C, D;
	wire F1, F2;
	
	circuit cmp1 (F1, F2, A, B, C, D);

	// setup data
	initial begin
		A = 0; B = 0; C = 0; D = 0;
		#79 $finish;
	end

	always #5 D = ~D;
	always #10 C = ~C;
	always #20 B = ~B;
	always #40 A = ~A;


	// output
	initial begin
		$display ("\t\tTIME\tA\tB\tC\tD\t|\tF1\tF2");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%b\t%b\t%b\t%b\t|\t%b\t%b\n", $time, A, B, C, D, F1, F2);
	end
endmodule
```
#### OUTPUT
![](https://i.imgur.com/ZOjNoDn.png)

### c. Implement it with dataflow modeling.
``` verilog
module circuit (output F1, F2, input A, B, C, D);
	wire T1, T2, T3, T4;
	wire NOT_B, NOT_A, NOT_D;

	// setup
	assign T1 = (~B) & C;
	assign T2 = (~A) & B;
	assign T3 = (A) | T1;
	assign T4 = (T2) | D;
	
	assign F2 = T2 ^ (~D);
	assign F1 = ~(T3 | T4);
endmodule
```
#### OUTPUT
![](https://i.imgur.com/ucKlk5o.png)



## EX02
### a. gate-level modeling
```verilog
module ha (output S, C, input x, y);
	xor (S, x, y);
	and (C, x, y);
endmodule

module circuit (output [3:0] C, input [1:0] A, B);
	wire t0, t1, t2, t3;

	// C0
	and (C[0], A[0], B[0]);

	// C1
	and (t0, A[0], B[1]);
	and (t1, A[1], B[0]);
	ha G1 (t2, C[1], t1, t0);

	// C2, C3
	and (t3, A[1], B[1]);
	ha G2 (C[3], C[2], t3, t2);
endmodule
```
![](https://i.imgur.com/zYFMIoz.png)



### b. data flow modeling
```verilog
module ha (output S, C, input x, y);
	assign S = x ^ y;
	assign C = x & y;
endmodule

module circuit (output [3:0] C, input [1:0] A, B);
	wire t2;

	// C0
	assign C[0] = A[0] & B[0];

	// C1, C2, C3
	ha 	G1 (t2, C[1], A[1]&B[0], A[0]&B[1]),
		G2 (C[3], C[2], A[1]&B[1], t2);
endmodule
```
![](https://i.imgur.com/qnqBiZG.png)



### c. write a testbench to verify a, b.
```verilog!
module test1_tb;
	reg [1:0] A, B;
	wire [3:0] C;
	
	circuit cmp1 (C, A, B);

	// setup data
	initial begin
		A = 0; B = 0;
		#79 $finish;
	end

	always #5 B[0] = ~B[0];
	always #10 B[1] = ~B[1];
	always #20 A[0] = ~A[0];
	always #40 A[1] = ~A[1];


	// output
	initial begin
		$display ("\t\tTIME\tA\tB\t|\tC");
		$display ("\t\t------------------------------------------------------------");
		$monitor ("%t\t%d\t%d\t|\t%d\n", $time, A, B, C);
	end
endmodule
```

測試結果在a, b裡有附了。
