---
# System prepended metadata

title: 'Design: Tunning I/V Convert(IVCvT) with OPA355'
tags: [HW-Circiut, Design, DeWei]

---

# Design: Tunning I/V Convert(IVCvT) with OPA355

## 1. Major circuit
![](https://i.imgur.com/1G0eI0g.png)

## 2. PD param

* [SFH250v](https://www.farnell.com/datasheets/3029078.pdf)
  * Capacitance: 11pF @1MHz
  * Photocurrent: 4.4uA @1uW/5VR
  * TR/RF max: 16ns @5VR
  * **Has fiber house and lock**
  	* This means we don't racking our's brains to desing house and lock
  		* 3D Printer?
  			* Does it realiable? lock is tight? well housing PD?
  			* Yield
  		* Plastic injection?
			* How to draw?
			* More time and more cost
		* cons: SFH250V is expensive
## 3. OPA param

|Param\\OPA| [OPA192](https://www.ti.com/lit/gpn/opa192) | [OPA810](https://www.ti.com/lit/gpn/opa810) |[LTC6268-10](https://www.analog.com/media/en/technical-documentation/data-sheets/626810f.pdf) | [OPA356](https://www.ti.com/lit/gpn/opa356) | 
| ------- | --------- | ---------- |----------- |----------|
| Ci-Comm |   6.4p    |    1.6p    |   0.45p    |   1.5p   |
| Ci-Diff |   2.5p    |    0.5p    |   0.1p     |   1.5p   |

   
## 4. Calc Gain-Bandwidth

### 4.1 Cin

![](https://i.imgur.com/y3tY4fY.png)
![](https://i.imgur.com/e4ayW7h.png)

* SHF250v
  * OPA192
    * Cin = Cj+Cd+Cm2 = 11pF + 6.4pF + 1.6pF  = 19pF
  * OPA810
    * Cin = Cj+Cd+Cm2 = 11pF + 2.5pF + 0.5pF  = 14pF
  * LTC6268-10
    * Cin = Cj+Cd+Cm2 = 11pF + 0.45pF + 0.1pF = 11.55pF
  * OPA356
    * Cin = Cj+Cd+Cm2 = 11pF + 1.5pF + 1.5pF = 14pF

### 4.2 Bandwidth

* **Bandwidth of system(circuit) is limited by *Cin* and *C1* and *R1***

$BW = \dfrac{1}{(2\pi)(R1)(Cin+C1)}$

### 4.3 To increase bandwidth

* Reducing R1?
	* Since Vo = (Ipd)(R1)
	* Vo will be reduced
		* If Vo<<<, then background/noise would cover your signal
		* For the low light application, we can't suggest this solution
* Reducing Cin?
	* Change OPA
	* Add negative bias for PD
		* This means we will get about 3 times BW
			* ![](https://i.imgur.com/Vu7sDpt.png)
		* Dual-rail power supply will increase complexity of circuit
			* Low-Noise LDO for negitive, which is rare and expensive
* Reducing C1?
	* I found minimum of MLCC is 0.1pF in the market



## Reference
* [1 MHz, Single-Supply, Photodiode Amplifier Reference
Design](https://www.ti.com/lit/ug/tidu535/tidu535.pdf)
* [LPF Calculator](http://www.learningaboutelectronics.com/Articles/Low-pass-filter-calculator.php)
* [LPF Plotter](https://www.trance-cat.com/electrical-circuit-calculators/en/rc-low-pass-filter-calculator.php)

###### tags: `Design` `DeWei` `HW-Circiut`