## Bi-Weekly Progress

https://charlestsai1729.github.io/AAML_test/labs/lab_2.html

https://github.com/charlestsai1729/AAML_test/blob/main/labs/Lab%201.md

最近都在弄ray tracing和實習的東西，之後盡量補回進度

下面的這個可以用iverilog

#==============================================================================#
# AIC2021 Project1 - TPU Design                                                #
# file: Makefile                                                               #
# description: Makefile for TPU testbench                                      #
# authors: kaikai ([e-mail])                                       #
#          suhan  ([e-mail])                                         #
#==============================================================================#

#------------------------------------------------------------------------------#
# Change your own verilog compiler.                                            #
#------------------------------------------------------------------------------#
# VERILOG=xrun
#VERILOG=ncverilog
VERILOG=iverilog

#------------------------------------------------------------------------------#
# Directories Declarations                                                     #
#------------------------------------------------------------------------------#
CUR_DIR=$(PWD)
TESTBENCH=TESTBENCH
RTL_DIR=RTL
SIM=vvp


verif1: clean
	python3 data_generator.py --mode 0 --target_dir verif1 --ncases 10
	cp verif1/input.txt verif1/input.bk
	mv verif1/input.txt $(TESTBENCH)/
	$(VERILOG) -o verif1/simulation $(TESTBENCH)/TESTBENCH.v -I $(TESTBENCH) -I $(RTL_DIR) -D RTL
	$(SIM) verif1/simulation +access+r

verif2: clean
	python3 data_generator.py --mode 1 --target_dir verif2 --ncases 10
	cp verif2/input.txt verif2/input.bk
	mv verif2/input.txt $(TESTBENCH)/
	$(VERILOG) -o verif2/simulation $(TESTBENCH)/TESTBENCH.v -I $(TESTBENCH) -I $(RTL_DIR) -D RTL
	$(SIM) verif2/simulation +access+r

verif3: clean
	python3 data_generator.py --mode 2 --target_dir verif3 --ncases 10
	cp verif3/input.txt verif3/input.bk
	mv verif3/input.txt $(TESTBENCH)/
	$(VERILOG) -o verif3/simulation $(TESTBENCH)/TESTBENCH.v -I $(TESTBENCH) -I $(RTL_DIR) -D RTL
	$(SIM) verif3/simulation +access+r

verif4: clean
	python3 data_generator.py --mode 3 --target_dir verif4 --ncases 100
	cp verif4/input.txt verif4/input.bk
	mv verif4/input.txt $(TESTBENCH)/
	$(VERILOG) -o verif4/simulation $(TESTBENCH)/TESTBENCH.v -I $(TESTBENCH) -I $(RTL_DIR) -D RTL
	$(SIM) verif4/simulation +access+r

clean:
	rm -rf verif*

## ~2024/8/8

### DEMO
1. 跟原本一樣隨時都可以約 demo
* Cons: 可能不一定約的到時間
2. 先交到 E3 上，看 E3 上的繳交時間評斷準時或遲交多久
* Pros: 判斷遲交時間方便、補 Demo 可以統一時間、可以抓抄襲?
* Cons: 學生多一個步驟麻煩、Demo 的 code 跟交到 E3 上的可能不一樣
3. 先交到 E3 上，Demo 時現場合成編譯
* Cons: 合成加編譯可能要超過 5 分鐘

Lab1 SPEC done
https://charlestsai1729.github.io/AAML_test/labs/lab_1.html
Lab3 SPEC done
https://charlestsai1729.github.io/AAML_test/labs/lab_3.html

然後 Lab3 寫好了

Lab4 SPEC half
https://charlestsai1729.github.io/AAML_test/labs/lab_4.html
測試 accuracy 的方式
TBD:
Evaluation Criteria
會不會太難 (add op, hardware design, fixed-point arithmetic, CFU handshake, softmax, op design)
提示會不會太多還是太少

lab5?

## ~2024/8/22

lab4 spec finish
https://charlestsai1729.github.io/AAML_test/labs/lab_4.html

modify the testing model to avoid hardcoding the answer (finished, generating the golden test)

lab5:
* fused layer:
1. I think it's impossible to achieve it by modifying the tflite model.
2. Without modifying the model (achieve by only modifying software kernel)
Maybe way too easy
* lab4, 5 in the last year
I'll try it this week.
* cancel, only four labs this year