---
# System prepended metadata

title: Computer Organization Course 2024

---

Computer Organization Course Syllabus



| Week	   | Course	  								  					  | Lab		 |
| -------- | -------------------------------------------------------------| -------- |
| 1	       | Technology Trends and Quantitative Analaysis for Performance | Lab 0    |
| 2	       | RISC-V Instructions Sets, Part 1 				      		  | Lab 1	 |
| 3	       | RISC-V Instructions Sets, Part 2  				  			  | 	     |
| 4	       | RISC-V Instructions Sets, Part 3  				  			  | 	     |
| 5	       | Arithmetic for Computers   			  			  		  | Lab 2    |
| 6	       | RISC-V Single-Cycle Implementation  						  | 		 |
| 7	       | RISC-V Single-Cycle Implementation		 	  				  |     	 |
| 8	       | Pipeline and Hazards   				  		              | Lab 3    |
| 9	       | Pipeline and Hazards   				  		  			  |  		 |
| 10	   | Midterm   				  		  			      			  | 	 	 |
| 11	   | Branch Predictor   				  		  		      	  | Lab 4	 |
| 12	   | Memory Hierarchy - DRAM					  	  			  | 		 |
| 13	   | Memory Hierarchy - Cache Organization   				  	  | 	     |
| 14	   | Memory Hierarchy - Cache Optimization  				  	  | Lab 5    |
| 15	   | Data-Level Parallelism   		  					  		  |		     |
| 16	   | Thread-Level Parallelism    		  						  |			 |
| 17	   | Final Exam					    		  					  |			 |




Lab

Lab 0 Environment setup (Ripes, Vivado)
Lab 1 Implement a simple cycle CPU
Lab 2 Implement R-type, I-type, and jump instruction
Lab 3 Implement a simple version pipelined CPU
Lab 4 Advanced pipelined CPU
Lab 5 Cache Simulator

-----

[Lab 0 Environment Setup & simple verilog practice](https://hackmd.io/8m-M6hv7Tj214ZiThI-e4A)
[Lab 1 Single Cycle CPU w/ Simple RISC-V Instruction](https://hackmd.io/@kairesearch/H1LUmDA5h)
[Lab 2 Single Cycle CPU w/ Branch Instruction](https://hackmd.io/@brianLiu45/rJo6iGw2h)
[Lab 3 Pipelining CPU](https://hackmd.io/@kairesearch/HJVf2Gv33)
[Lab 4 Data/Control Hazard](https://hackmd.io/@kairesearch/SJ4-5uo33/edit)
[Lab 5 Implement Cache Simulator](/yDY5wPX4QNyQ02UcyZ2Vwg)

Lab1 4 week
- Implement a simple cycle CPU
- Implement R-type, I-type, and jump instruction

Lab2
- Basic: Implement a simple version pipelined CPU
- Advanced: advanced instruction pipelined CPU 

Lab3
- Basic: Implement LRU, FIFO Cache Sim
<!-- - Advanced: Non-Blocking Cache -->



