---
# System prepended metadata

title: FIDO Accelerator
tags: [Accelerator]

---

# FIDO Accelerator
###### tags: `Accelerator`
###### members: @cjamhe01385 


## Topic
A design for improving the throughput of FIDO protocol on IOT using CGRA.

## Introduction
[Summary](/DqnEFvoKRJSBP1IByfVqxg)

### Challenges
1. We need to deal with a large number of requests at a short time, so how to run multiple requests parallelly?
2. FIDO protocol supports **multiple** asymmetric cipher algorithms (e.g. ECDSA, RSA) which are the bottleneck of process. Can we accelerate all supported algorithm to reduce the impact?

### Goals
- Using CGRA reconfigurable feature to accelerate all supported algorithm in FIDO flow. 
- Processing multiple requests parallelly to increase the throughput.
- Reuse memory for some constant values.

### Ideas
- Considering a low power design refer to [SNAFU](http://www.cs.cmu.edu/~beckmann/publications/papers/2021.isca.snafu.pdf)

### Background
[Algorithm & Data Graph](/DqnEFvoKRJSBP1IByfVqxg)

### Related Work
1. [Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems](https://www.researchgate.net/publication/258380670_Prime_Field_ECDSA_Signature_Processing_for_Reconfigurable_Embedded_Systems)
2. [Cost-Efficient Parallel RSA Decryption with Integrated GPGPU and OpenCL](https://ieeexplore.ieee.org/document/7816897)
3. [An Efficient Elliptic Curve Cryptography Signature Server With GPU Acceleration](https://ieeexplore-ieee-org.ezproxy.lib.nctu.edu.tw/stamp/stamp.jsp?tp=&arnumber=7555336)
4. [Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor](https://ieeexplore.ieee.org/abstract/document/4580186)

## Progress
2022/02/16 - how to map data into CGRA?
[2022/03/03 - find a method and simulation for performance measurement](/RclsnRdpTKKVoh36QCiUNw?view)
[2022/03/17 - performance measurement of baseline cases](https://hackmd.io/SpL8NuMNSbKTk5FFzKCRZA?view)
[2022/04/07 - load imbalance measurement](https://hackmd.io/eOTXPpMyTAqnczZA3vzEbA)


## References
1. Architecture for Dynamically Reconfigurable Embedded Systems
2. [DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures](https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.6251&rep=rep1&type=pdf)
3. [Are Coarse Grain Reconfigurable Architectures Suitable for Cryptography](https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269699/document)
4. [A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications](https://dl.acm.org/doi/fullHtml/10.1145/3357375)
5. [DiAG: A Dataflow-Inspired Architecture for General-Purpose Processors](http://Users/cheriehsieh/Downloads/3445814.3446703.pdf)
6. [SNAFU: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture](http://www.cs.cmu.edu/~beckmann/publications/papers/2021.isca.snafu.pdf)
7. [gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling](https://www.microarch.org/micro53/papers/738300a471.pdf)