# RISC-V Accelerator ###### tags: `Accelerator` ###### member: @劉家瑋 @洪珩鈞 ###### meeting: Wed-13:00 :::spoiler 目錄 [TOC] ::: --- ## 進度報告 * https://hackmd.io/ZnT7tOdfReqqy576E6VHMw ## Github * 待補 ## 架構總結 * https://hackmd.io/nmRQU4cfSO-ZX0dkmqgc9w --- ## 環境架設 #### riscv-toolchain: https://hackmd.io/RVWzls-_SdK72BHR2S51rg #### spike + pk: https://hackmd.io/6f76vg-VT1GqVhJ_m2E1LA #### LLVM: https://hackmd.io/0XsFB90_SeWg9dMLE9U-4g #### RISCV V-Extension & Benchmark: https://hackmd.io/-yYvJ5SoSgyr_O2_Ei_FQg #### QEMU: https://hackmd.io/6z9nQu2QSY22ROiV-Op6OA #### Build RISC-V tools: (same as ICMR on IP.136) (riscv-toolchain + spike + pk + LLVM + RVV-benchmark) * https://hackmd.io/VtxTkJV-SP-N3JpE4AOuMg #### Build QEMU: * https://hackmd.io/@nx1bTzFpQvaKD_yxYRmBaQ/S1l4siGA_ #### Build RISC-V tools: (by Tom Lin)(riscv-toolchain + spike + pk) * https://hackmd.io/@nx1bTzFpQvaKD_yxYRmBaQ/Skpx_8tSO #### How to simulate custom instruction * https://hackmd.io/ZsI50YxrQhKRHUF6gZswQA?both #### Build Vivado and run Aquila on NEXYS-VIDEO * https://hackmd.io/EKC_5i4vQ6GLcMvKyK9dFQ #### Build VCS and run Rocket-Chip on NEXYS-VIDEO * https://hackmd.io/VCo4E8aXQgWMCIxzt7gJiA --- ## 教學及參考資料 #### RISC-V * http://crva.ict.ac.cn/documents/RISC-V-Reader-Chinese-v2p1.pdf.11.3 #### RISC-V spec * https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (p.105) #### RISC-V Vector Extension * https://www.youtube.com/watch?v=oTaOd8qr53U&ab_channel=AndesTechnology #### Modeling Deep Learning Accelerator Enabled GPUs (Paper summary) * https://hackmd.io/D0dKHBkbR2C8XKr63zRH8w #### RISC-V CPU: * https://github.com/ic-lab-duth/RISC-V-Vector (V extension supported ) * https://hackmd.io/7dJ1VdmzRNqaWr7YTWGUiw (Paper summary) * https://github.com/chipsalliance/rocket-chip (V extension supported ) * https://github.com/eisl-nctu/aquila * https://github.com/stevehoover/warp-v #### Hwacha Vector-Thread Co-Processor Sources * https://github.com/ucb-bar/hwacha #### Rocket-chip CPU(open source RISC-V CPU support V extension) * https://zhuanlan.zhihu.com/p/140360043 #### RISC-V^2: A vector processor core for the RISC-V Vector ISA extension * https://ieeexplore.ieee.org/document/9181071 #### RISC-V GPGPU verilog * https://github.com/vortexgpgpu/vortex #### RISC-V vector register programming * https://gms.tf/riscv-vector.html