# CAN Transmission
###### tags: `firmware_hardware` `electrical_system` `NTURT`

## FDCAN timing configs

Follow the instruction of this [video](https://youtu.be/kXyzaaSk6Qs?t=558) to use the bit timing calculator from this [website](https://www.kvaser.com/support/calculators/can-fd-bit-timing-calculator/). There are couple parameters to mention:
- Clock tolerance: **20ppm** or **50ppm**
The X3 crystal used for nucleo-64 board HSEs have tolarences of **20ppm**, while the X1, X2 crystals for nucleo-32 and nucleo-144 are **50ppm**.
> The tolarences of the crystals are from the BOMs of the boards.
- Node delay: **420ns**
The can transceiver we're using is [CTM1051(A)M](https://www.lcsc.com/datasheet/lcsc_datasheet_1809191824_ZLG-Zhiyuan-Elec-CTM1051AM_C91274.pdf) and it's propagation delay is **420ns**.

### FDCAN high priority message

STM32 fdcan provide interrupt that can be trigger when high priority messages, which are configured using filters, are received. However, such high priority message can not be stored to a rx buffer, only can be a rx fifo. Since the intention of high priority message is to get the message as soon as possible, and not to be queued by a fifo. Such limitation renders the functionality useless.

> The desired high priority behavior can be achieved by enabling the receive interrupt of fifo1 and only send high priority message to fifo1.

### FDCAN timestamp counter

STM32 fdcan provide 16-bit hardware timestamp counter for each received frame. The counter clock source can be from two sources, one from internal can bit timing [^1] and another from external timer TIM3 [^2].

From internal source, fdcan provides prescaler up to 16, the counter still wraparounds within seconds. The same also applies to TIM3 since it only has 16-bit prescaler.

> Although fdcan provides timestamp wraparound interrupt to address such issue, it's such a hassle since it can no longer only depends on hardware and it further complicates settings. Such finctionality is not used.
Instead, the timestamp is provided by 32-bit TIM2 with $10\mu s$ counter devided by 100. Such timer is also used for freertos stats and will only wraparound every 11 hours.

[^1]: CAN bit timing is the same as the can bitrate, such as 1M bitrate will have can bit timing of $1\mu s$. However, when enabling flexible datarate, the can bit timing also varies, making this soure undesirable. (reference from stm32 reference manual, regarding FDCAN_TSCC)
[^2]: Reference from stm32 reference manual, regarding FDCAN_TSCC, only checked stm32h723 and stm32g4.

### FDCAN timeout counter

STM32 fdcan provide 16-bit hardware timeout counter with the same clock source as timestamp counter, that triggers an interrupt when counter reaches zero. However, it only supports tx event fifo and two rx fifos.

> Since the timeout timer only supports limited fifo, such functionality is not used.
Instead, the timeout is provided by 32-bit TIM2 with $10\mu s$ counter devided by 100. Such timer is also used for freertos stats and will only wraparound every 11 hours.

## FDCAN Implementation on STM32

### Loopback Mode
#### The MX Setup
This section is going to be very large, as we will cover the cubeMX setup, along with a huge number of parameters and the reasons behind their values.
Choosing the 64 Mhz internal clock in this tutorial. The reason for the same will be explained in a while. Also note that the FDCAN clock is 50 Mhz. This will be used in the later part.


using the transs