---
# System prepended metadata

title: ECE 4530/5530 Lab 2a

---

:::info
# ECE 4530 Lab 2a

> [name=Nikolai Nekrutenko (nan34), Sarah Hawes (ssh93)]
:::

## 1. Table of small signal parameters

|  | NMOS - Plots | NMOS - DC Op Pts | PMOS - Plots | PMOS - DC Op Pts |
| -------- | -------- | --- | --- | -------- |
| $V_{TH} [V]$ |  0.5V  | 0.584V | -0.5V     |  -0.557V  |
| $g_m [\mu S]$ | 832 μA/V (dc); 879 μA/V (ac) | 728 μA/V | 510 μA/V (dc); |   448μA/V  | 
| $r_o [k \Omega]$ | 24 kΩ (dc); 22.7 kΩ (ac) |  22.6kΩ  | 58.3kΩ | 44.6kΩ         |
| $c_{gs} [fF]$  |  0.573 fF  | 0.61 fF    | 0.21fF | 0.195fF |
| $c_{gd} [fF]$ | 0.191 fF; 0.151 fF; 0.148fF | 0.148 fF | 0.60 fF; 0.569fF; 0.605fF |  0.605fF   |
| $c_{db} [fF]$ | 0.24 fF | 83.4zF  | 0.22fF | 0.052fF |

**For NMOS case from plots calculations:**

We assume: V_od = 200 mV = Vgs - Vth

From *Figure 1.3* in the *Appendix*, we see that the estimated Vth = 500 mV as it lies in between exponential and square law.

Thus, the estimated bias Vgs = 500 mV + 200 mV = 700 mV

We are given that: Vgs = Vds = Vth + 200 mV (Vgs = Vds = 700 mV) in step 17. This implies that the MOSFET is operating in saturation mode. $g_m$ and $r_o$ can thus be estimated:

$g_m = \frac{2Id}{Vod} = 2 \cdot 83.197 \mu A/(200 mV) = 831.97 \mu A/V$

$r_o = 1/g_{ds} \approx 1/(\frac{87.5µA - 80µA}{0.8V - 0.62V}) = 24kΩ$

For a calculation of the capacitances for NMOS from the small signal model, please see work below:

![Lab 2a - page 1](https://hackmd.io/_uploads/HkdHojxlye.png)

Cgs = 5.73 x 10^-16 F and was derived form equation below:

$c_{gs} = 1/wZ_{gs}$

$|Z_{gs}| = V_g/(I_G - I_D) = V_g/I_D = 1/(5.1mA - 1.32mA) = 265 \Omega$

$c_{gs} = 1/wZ_{gs} = 6.0*10^{-16}F$

Looking at the graph of Id vs Frequency (*Figure 2.3*), we can see that at lower frequencies, the slope of Id vs w is constant as this is far below the frequencies of the capacitors taking into effect.

@ Freq = 1Mhz, Id ~ 44*10^-6 A and Vds = 1 volt

Therefore using $V = IR$: 
$r_o = V_{ds}/I_d = \frac{1V}{44 \cdot 10^{-6} A} = 22.7kΩ$

With this in mind, we can calculate Cdb and Cgd:

$2.5mA = I_{Cdb} + I_{Cgd} + \frac{V_{ds}}{r_o}$

$I_{Cdb}$ = 1.51 mA @ 1 THz
$C_{db} = \frac{1.51mA}{(2\pi \cdot 1\text{THz})}  2.4 \cdot 10^{-16} F$
$C_{gd} = \frac{0.95mA}{(2\pi \cdot 1\text{THz})} = 1.51 \cdot 10^{-16} F$

Note, the calculations for PMOS are done in a similar way, as all of the steps in the lab are repeated in the same way, apart from changing the nfet to be a pmos rather than nmos. The PMOS calculations from the plots (in the Appendix) are shown below:

$g_m \approx 2 \cdot 51uA / 0.2V = 510uA/V$

$r_o \approx 1/[(54uA - 51uA)/(0.875V - 0.7V)] = 58.3k \Omega$

$c_{gd} = 1/wZ_{gd}$

$|Z_{gd}| = V/I = V_g/I_D = 1/1.32mA = 758 \Omega$

$c_{gd} = 1/wZ_{gd} = 2.1*10^{-16}F$

$c_{gs} = 1/wZ_{gs}$

$|Z_{gs}| = V_g/(I_G - I_D) = V_g/I_D = 1/(5.1mA - 1.32mA) = 265 \Omega$

$c_{gs} = 1/wZ_{gs} = 6.0*10^{-16}F$



## 2. Estimated values

|                       | NMOS | PMOS |
| --------------------- | ---- | ---- |
| $\mu [Am^2/(V^2F)]$   |  4.40 * 10^-3  | 4.27 * 10^-3 |
| $c_{ox} [fF/\mu m^2]$ |   61.6   |   54.6   |
| $c_{ol} [fF/\mu m]$   |   0.592   |   2.42   |
| $C_{j} [fF/\mu m]$    |   0.00033   |  0.208 |

As mentioned in the second step of the lab, width W was set to 0.250um and length L to 45 nm.

The following equations were used to compute the values:

$C_j = \frac{C_{db}}{W}$

$c_{ol} = \frac{C_{gd}}{W}$

$C_{gs} = C_{gd} + \frac{2}{3}WLc_{ox}$

$c_{ox} = \frac{3(C_{gs} - C_{gd})}{2WL}$

$I_d = \frac{1}{2}\mu c_{ox} \frac{W}{L} (V_{gs} - V_{th})$

$\mu = \frac{2I_DL}{c_{ox}W(V_{GS} - V_{TH})}$

The relationship between ${I_D}$ and ${V_{GS}}$ was found from *Figure 1.3*. We chose ${V_{GS}}$ = 0.75V which corresponds to a current of 125uA.

## 3. Common Source Amplifier

We adjusted the transistor parameters and bias point (by adjusting Vdd) to get the amplifier to meet the specifications. In particular, we sequentially increased and decreased the vdc component of vdd until we found the optimal value to meet our required specifications, we found 1.3 volts to be the optimal value. Additionally, we modified the lengths of the transistors and found 45n to be the optimal value, and widths of 60um for the left-most and 6um for the right-most respectively.

Below is a screenshot of the CS amplifier schematic with DC voltages annotated:

![Screenshot 2024-10-10 at 15.20.16](https://hackmd.io/_uploads/SkU_Oilekg.png)


Figure 3.1: Magnitude of AC response of $V_d$ (in green) and $V_g$ (in pink) vs $log(w)$
![CS_Amp_AC_Mag_drain_gate_vs_w_in](https://hackmd.io/_uploads/H1khwLggJx.jpg)

Figure 3.2: Transient response of $V_{in}$ (in green) and $V_{out}$ (in pink)
![CS_Amp_trans_resp_Vin_Vout](https://hackmd.io/_uploads/HkknwLelkg.jpg)

Figure 3.3: Magnitude and Phase AC response of $V_{out}$ vs $w$
![CS_Amp_Vout_vs_w_in](https://hackmd.io/_uploads/Sy13vIeg1e.jpg)

CS amplifier power estimate:

As in the screenshot above of the amplifier, we can see that the current flowing through the dc source is 11.4mA, and the voltage is 1.3V. Thus, the power consumed is P = IV = 14.8mW.



## Appendix: Plots for NMOS & PMOS

The plot below was used to find $g_m$ from: 

![Screenshot 2024-10-18 at 6.41.02 PM](https://hackmd.io/_uploads/HyhbVwlxkl.png)

### Section 1: NMOS Plots

Figure 1.1: $log(I_d)$ vs $w$
![NMOS_Id_vs_Vgs_w_log](https://hackmd.io/_uploads/HkaXBLglye.jpg)

Figure 1.2: $I_d$ vs $log(w)$
![NMOS_Id_vs_Vgs_w](https://hackmd.io/_uploads/HyoXI8ge1g.jpg)

Figure 1.3: $I_d$ vs $V_{gs}$
![NMOS_Id_vs_Vgs](https://hackmd.io/_uploads/S1TmrLxeke.jpg)

Figure 1.4: $I_g$ and $I_d$ vs $w$ with AC drain - go back and take a look at
![NMOS_Ig_Id_vs_w_AC_drain](https://hackmd.io/_uploads/r1AmrIelJl.jpg)

Figure 1.5: $I_g$ vs $w$
![NMOS_Ig_vs_w_log](https://hackmd.io/_uploads/r1RmHIelyg.jpg)

### Section 2: PMOS Plots

Figure 2.1: $I_d$ vs $V_{ds}$
![PMOS_Id_vs_Vds](https://hackmd.io/_uploads/rkvYwLelyg.jpg)

Figure 2.2: $I_d$ vs $V_{gs}$
![PMOS_Id_vs_Vgs](https://hackmd.io/_uploads/SyLFwUxeJx.jpg)

Figure 2.3: $log(I_d)$ vs $log(w)$
![PMOS_Id_vs_w_bothlog_v3acm1](https://hackmd.io/_uploads/HJwtDLelyl.jpg)

Figure 2.4: $I_d$ vs $V_{gs}$ - come back to renaming this one
![PMOS_Id_vs_w_bothlog](https://hackmd.io/_uploads/r1uFw8lxyg.jpg)

Figure 2.5: $I_d$ vs $w$
![PMOS_Id_vs_w_nolog](https://hackmd.io/_uploads/HJdYDLel1l.jpg)

Figure 2.6: $I_d$ vs $log(w)$
![PMOS_Id_vs_w](https://hackmd.io/_uploads/B1_YP8ll1x.jpg)

Figure 2.7: $log(I_g)$ vs $log(w)$
![PMOS_Ig_vs_w_bothlog_v3acm1](https://hackmd.io/_uploads/BJOYDIggJg.jpg)

Figure 2.8: $log(I_g)$ vs $log(w)$
![PMOS_Ig_vs_w_bothlog](https://hackmd.io/_uploads/SJ_KwIegye.jpg)

Figure 2.9: $I_g$ vs $w$
![PMOS_Ig_vs_w_nolog](https://hackmd.io/_uploads/rJuFPLxxJl.jpg)

Figure 2.9: $I_g$ vs $log(w)$
![PMOS_Ig_vs_w_onelog](https://hackmd.io/_uploads/Bk_YwLxekg.jpg)



