# SARA: Scaling a Reconfigurable Dataflow Accelerator

###### tags: `Accelerators`
## Abstract
The need for speed in modern data-intensive work-loads and the rise of “dark silicon” in the semiconductor industryare pushing for larger, faster, and more energy and area-efficient architectures, such as Reconfigurable Dataflow Accel-erators (RDAs).
To address these challenges, we present SARA, a compilerthat employs a novel mapping strategy to efficiently utilize large-scale RDAs.
Starting from a single-threaded imperative abstrac-tion, SARA spatially maps a program onto RDA’s distributedresources, exploiting dataflow parallelism within andacrosshy-perblocks to saturate the compute throughput of an RDA.