# WG7 ###### tags: `Spec` # O-RAN.WG7.DSC.0-v02.00 ## Deployment Scenarios and Base Station Classes * Deploy Scenarios ``` eMBB URLLC ``` * Base Station Architecture: Background * Split Architecture * Integrated architecture ## Split Architecture ![Split Architecture](https://i.imgur.com/Fli9kUj.png) * Note that the term optional is used to indicate there may be a deployment case where a switch or FHGW may not be needed * O-CU shall be located at the data center and O-DU can be placed either at the data center or at the cell site * following three criteria ```txt * O-RAN WG4 (open fronthaul interface group) released interfaces * O-RAN approved publicly (e.g., small cell forum or etc.) available external interfaces * Fronthaul interfaces made available and published as part of an O-RAN approved WG7 reference design ``` * associated terminologies will be used throughout all WG7 specifications * O-DU~7-2~ ↔ FHGW~7-2→8~ ↔ O-RU~8~ * where the fronthaul gateway does not perform a protocol translation * O-DU~6~ ↔ FHGW~6~ ↔ O-RU~6~ * O-DU~7-2~ ↔ FHGW~7-2~ ↔ O-RU~7-2~ * O-DU~8~ ↔ FHGW~8~ ↔ O-RU~8~ (split finction is in wg4) * split function * Split option 6 * All PHY functions will reside in O-RU~x~ while MAC functions will be performed in O-DU~x~. In other words, only un-coded user data is on FH. In this case the terminology O-DU~6~ and O-RU~6~ is used. * Split option 7-2 * the PHY is split into High and Low PHY functions where High PHY functions (coding, rate matching, scrambling, modulations and layer mapping) are performed in O-DU~x~ while O-RU~x~ performs the Low PHY functions (precoding, remapping, digital beamforming, IFFT and CP insertion). All I/Q samples are in frequency domain. In this case the terminology O-DU~7-2~ and O-RU~7-2` is used * split option 8 * All PHY functions are performed in O-DUx. This means that O-RU~x~ function is limited to RF to baseband conversion and vice versa. The I/Q samples on FH interface are in time domain. In this case the terminology O-DU~8~ and O-RU8 is used. ![integrated Architecture](https://i.imgur.com/E5ThO28.png) ## Deployment Scenarios ### Indoor Picocell ![Indoor Picocell](https://i.imgur.com/7xW96pF.png) ### Outdoor Picocell ![Outdoor Picocell](https://i.imgur.com/AUXMuxp.png) ![Outdoor Picocell](https://i.imgur.com/OXT9FTZ.png) ### Outdoor Microcell ![](https://i.imgur.com/ieZrKIR.png) ![](https://i.imgur.com/0MAmhgL.png) ### Integrated access and backhaul (IAB) ![](https://i.imgur.com/NELlR3b.png) ![](https://i.imgur.com/ttrm5t2.png) ### Outdoor Macrocell ![](https://i.imgur.com/we0HoIL.png) ## Base Station Type Classification ![](https://i.imgur.com/Rh85KDD.png) ### Indoor #### split function ![](https://i.imgur.com/SXfIIKg.png) #### The integrated architecture ![](https://i.imgur.com/smq0XRd.png) ### Outdoor #### Picocell ![](https://i.imgur.com/ahiWgOO.png) #### Microcell ![](https://i.imgur.com/05cNaAZ.png) ![](https://i.imgur.com/mtueYBk.png) ### Integrated access and backhaul (IAB) ![](https://i.imgur.com/eBcF3gj.png) #### Macrocell ![](https://i.imgur.com/LBO0D47.png) ### Key performance indicators #### peak data rate ![](https://i.imgur.com/NrAP9nu.png) #### Peak spectral efficiency * Peak spectral efficiency (bps/Hz) = Peak data rate (bps)/ bandwidth (Hz). ![](https://i.imgur.com/ERLxv9r.png) #### Bandwidth ![](https://i.imgur.com/jiDUFNg.png) #### Control plane latency ![](https://i.imgur.com/rpzUGWO.png) #### User plane latency ![](https://i.imgur.com/9ZIGfT8.png) #### Mobility ![](https://i.imgur.com/zGUZq84.png) # O-RAN.WG7.FHGW-HRD.0-v01.00 ### O-RAN White Box Hardware Working Group Hardware Reference Design Specification for Fronthaul Gateway * split architecture ![](https://i.imgur.com/sRVlVNi.png) * FHGW (Fronthaul Gateway) may be placed with the following O-RAN specified interfaces * The interface between O-DU and FHGW is Open Fronthaul (Option 7-2x). * The interface between FHGW and RU is an LLS option specified by O-RAN. * The interface between FHGW and RU may not support Open Fronthaul (Option 7-2x). ![](https://i.imgur.com/AioxEYB.png) * Low PHY function in the fronthaul gateway converts the CPRI/low level split interface between the RU and Open Fronthaul (Option 7-2x). * using a packet-based network ### ![](https://i.imgur.com/LC3LVhF.png) ```txt * point-to-point direct connect * mesh connect through other network element ``` ![](https://i.imgur.com/58lcZaX.png) * need two interfaces for connectivity towards the O-DUs ### low PHY function 1) FFT/IFFT (Lower-PHY DL/UL) 2) PRACH detection (Lower-PHY UL) 3) Handling of C-Plane/M-plane messages 4) Timing and synchronization of RU 5) eCPRI framing/de-framing and switching 6) CPRI framing/de-framing and switching 7) CPRI to eCPRI conversion 8) I/Q compression on eCPRI and CPRI links ### Timing * WG4 CUS specification * uses SyncE and PTP to provide frequency, phase and Time-of Day to necessary endpoints. ![](https://i.imgur.com/SetJcAx.png) ## Hardware Architecture and Requirements * In case of a FHGW, the combination of RU and FHGW acts as an O-RU ![](https://i.imgur.com/qNXhM8q.png) * Network Processing Unit * provides the packet transport functions of the FHGW. * Radio Signal Processor/Accelerator * from the low-level split-8 to O-RAN fronthaul interface (Split 7-2) * implements the Low PHY capabilities mentioned in section * can be implemented using a FPGA, DSP engine or ASICs * CPU * controls the transport capabilities and the Radio software which controls the radio signal processor * Memory * used to store the runtime data and software for the NOS and Radio software * Storage * store operating system, application software, firmware, operational status of Fronthaul Gateway * Timing Components * used to implement IEEE 1588 PTP and Synchronous Ethernet functionalities. * key components * GNSS * OCXO * DPLL * Servo * GNSS * Global Navigation Satellite System provides Time of the Day and Synchronization pulse (PPS) to the timing module to recover the clock and phase * OCXO(Oven controlled crystal oscillator) * provides the stable reference clock to the timing module with reference to which the PTP clock is generated * used to validate the other recovered clocks are within the required PPM offset or not * DPLL(Digital Phase lock loop) * generate the PTP clock steered by the servo algorithm * ensures that the generated clock meets the required specifications in terms of Jitter * Servo * analyses the timestamps from the ethernet packets, performs appropriate filtering and steers the DPLL to generate the PTP clock and Phase alignment of the clock to the primary clock source. * Ethernet PHY * physical level ethernet connectivity ### FHGW~7-2→8~ ![](https://i.imgur.com/ZOIVgCR.png) ![](https://i.imgur.com/P5fRZ49.png) ORAN traffic = [12 (AxCs) x 14 (symbols) x 1200 (REs) x 32 (bisIQ) ] / 1 ms + C/S/M-plane + Pkt_headeroverhead ~ 6.5 Gbps ![](https://i.imgur.com/SeL9q5b.png) ![](https://i.imgur.com/u89mb4N.png) * A reference clock signal to the NPU and FPGA at predetermined frequency from PTP domain * A One-Pulse per Second (PPS) reference signal where the transition from low to high as sampled by the clock * A lower speed bus carrying the seconds value of Time of Day. The 48 bits of seconds value is provided serially on this signal. ![](https://i.imgur.com/PPA0rbo.png) * Scalability and flexibility * red line is Scalability and flexibility