---
# System prepended metadata

title: Week 2- Questions

---

## Week-2 Questions

### Topic 1 : axi
#### Question : Design the interface logic between AXI and SRAM using minimum hardware resource, and draw timing waveform

```verilog=
// AXI Bus interface
input AWVALID
output AWREADY
input WADDR<31:0>

input WVALID
output WREADY
input WDATA<31:0>

input ARVALID 
output ARREADY 

output RVALID
output RDATA<31:0>
```
```verilog=
//SRAM
output DataIn <31:0>
output Address <31:0>
output EN
output WE
input DataOut<31:0>
```

`Axi` interface has the below relation. Read and write channel are independent, also, they can work concorrently.
![image](https://hackmd.io/_uploads/r1MVD0-jJx.png)

**Flow** : 
1. By the write channel, the master writes the address first, followed by the data. The address and data are stored in registers, and the system waits for `EN = 1` and `WE = 1` before sending them to SRAM.
2. By the read channel, the address is read in, indicating the data that master wants to retrieve. The slave accesses SRAM to fetch the corresponding data. Once the data is prepared, it is sent back to the master.

**Write channel**
![image](https://hackmd.io/_uploads/Sk2LeJziJl.png)

**Read channel**
![image](https://hackmd.io/_uploads/H1HSmJMiJl.png)

**Block diagram**
![image](https://hackmd.io/_uploads/rkfGnXK6yl.png)

---
#### Question : How to handle different access order from CPU and IO
![image](https://hackmd.io/_uploads/B11g4yfsJe.png)

**DMA** enables high-speed data transfer directly between devices and memory, improving efficiency and reducing CPU load, especially in data-intensive applications.

**DRAM** is a high-density and cost-effective memory used in computers for storing active data, though it needs to be refreshed regularly.

DMA enhancing data transfer efficiency, while DRAM offers large, affordable memory storage solutions. 

---
### Topic 2 : IO cache
#### Question : TPH Implementation options
![image](https://hackmd.io/_uploads/S1qKkL4jkl.png)



**Speculate Read DRAM (TPH=00):** Bi-directional access allows speculative checks in both cache and DRAM.

**Cache Hit & Dirty (TPH=10):** The target handles writing back dirty data to maintain coherency.

**Cache Hit & Not Dirty (TPH=01):** The requester supplies clean data directly from its cache.

**Invalidate Cache (TPH=10):** Target ensures cache invalidation for coherency.

**Write Update Cache (TPH=11):** Target with priority ensures high-priority cache updates.

**Write Allocate Cache (TPH=01):** Requester allocates cache space for write operations.
