# DAC80502 : Idiosyncrasies and Implementation

> [!Note] Scope
> Information presented below applies to 1-channel devices DAC60501, DAC70501, DAC80501, 2-channel devices DAC60502, DAC70502 and DAC80502.
> They're also pin-compatible.

> [!Warning] Lack Of Ability To Read Registers
> The 4-/8-channel versions DACx0504(DACx0508) provide a pure 4-wire SPI connection. If you intend to use the 1-/2-channel devices with SPI, adding a DAC80504 footprint parallel to the DACx0502 on your first revision will allow you to read back from a **register-compatible** device during development.
> 3-wire SPI on the 1-/2-channel implies SDIN is input-only, despite the table listing it as "input/output" at first glance.

The DACX0502 datasheet and others in the DACX050X family have left a trail of users on e2e.ti.com that struggle to achieve easy success when adding these DACs to their designs.
In hindsight, this is due to missing and unclear instructions.

<!-- In other words: if spending much more time reading the same document leads to opposite insights compared to skimming it, it's a dark pattern. //-->


The collection of various aspects below has been compiled hoping to help remove such obstacles.

One of the key issues with 3-wire SPI devices is that you'd want to leverage read operations during initialization
- for reading DEVID
- automatic detection of the DAC variant (12, 14 and 16 bit versions are pin compatible),
- reading the VREF Alarm flag,
- for interface benchmarking, since at high Baud rates, PCB stackup / trace capacitance will affect whether logic level requirements can be met,

but it appears that for such bring-up, only I2C register access will work, and interface benchmarking will have to be done indirectly. The author found that output of a sine or sawtooth waveform at different SPI clock frequencies and selected board temperatures is the most comprehensive approach to benchmarking when transfer errors start cropping up, as they show up as missed samples creating plateaus / jumps in the analog waveform.

## Bypass Capacitors

The write-up below assumes the hardware is already available, but let's get the supply bypassing part out of the way. As far as values, the guidelines are incomplete:


- Elsewhere in the datasheet: "use a minimum 150-nF capacitor between the reference output and AGND." (this should probably read "(combined) capacitance")
- in the [DAC80502EVM User Guide](www.ti.com/lit/pdf/SLAU818) a 100nF + 10µF polarized capacitor combination is recommended (use polymer tantalum or larger 10-47µF MLCCs in conjunction with 100-220 nF MLCC near the DAC).

## I2C

For completeness, the I2C interface is also mentioned, but not further utilized within the scope of this document.

I2C uses a 4-byte, MSB-first format with the 8-th bit of the first byte containing the R/!W flag. The upper nibble of the following Command byte is 0b0000.

## SPI

Most of the datasheet elaborates on I2C, with occasional mention of SPI details.

The interface is selected through SPI2C (actually I2C/!SPI, since SPI2C=0 selects SPI) logic level at power-on. Switching the interface mode between transfers is not implied, and doing so is discouraged where it states, "The SPI2C pin must be kept static after device powers up".
It's plausible to associate this requirement with peripheral state machine reset schemes that are tied to power-on reset.
There might however be some undocumented behavior that allows transitioning SPI2C around a soft reset. This has not been further explored by the author, but could lead to an ability to interrogate the DACX0501/2 device via remapped or bit-banged I2C before transitioning to SPI without a full power-cycle.
A p-channel MOSFET can be added to the design to perform a true power-cycle on the DAC if needed.
Either form of reset also discards the register contents, limiting its usefulness.

Setting up STM32G4 peripherals to generate the appropriate Mode-1 SPI transfers in a non-blocking, performance-oriented manner is detailed here: https://hackmd.io/@mrhw/BySiAvzBle

SPI uses a 3-byte, MSB-first format, and here the first bit (MSB) contains the R/!W flag. Repeated mentions in the context of I2C flag R/!W set the stage for assuming this flag is fully functional. Under 3-wire SPI mode, the datasheet should state "Bit 23: reserved, must write 0. SPI R/!W = 1 is supported in DACx0504, DACx0508 devices only."

The lower 7 bits of the Command byte as well as the 16 bit of register data to be written are arranged in an identical fashion.

To make matters worse, in Table 6-1, SDIN is listed as "Input/Output" but declared input-only in the context of SPI. No read timing or read operation format is given. Contrast that to [DACX0504](https://www.ti.com/lit/ds/symlink/dac70504.pdf) which has an extra SDO pin, and DACX0502 can be found to not support read operations in SPI mode.

A viable alternative has been proposed on the [e2e.ti.com](https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/968246/dac80501-spi) forum: set the bit to disable the internal reference, measure the bypass capacitor voltage to confirm the command has been received in the correct order, and that transfer has not been aborted. E.g. turn the reference on and off in a loop with some delay.

On the bright side, the DAC Data bits (written to BROADCAST, DACA_DATA, DACB_DATA) are MSB-aligned, so no bit shift operations are needed when downgrading to a lower-resolution device and vice versa.

### SPI Timing and Speed

While SPI mode-1 (CPOL=0, CPHA=1 aka "2nd edge") is only mentioned towards the end in a code snippet, Figure 1 at least gives away that data is clocked in at the SCLK falling edge:


The level of SCLK at !SYNC falling edge can be very confusing as well. One could be led to believe that SCLK would need to be high around the !SYNC falling edge, which is not the case.
- t\_syncs only relates to the first falling edge.
- t\_syncignore also relates to falling edges only.
- SCLK = 0 at !SYNC falling edge is valid.
- There's no limit how long pauses between individual clock pulses can be.
- !SYNC rising edge before the 24th SCLK falling edge aborts the transfer.
- Shift register data is transferred into registers at !SYNC rising edge, so it's not sufficient to toggle !SYNC at the start of a transfer and follow with 24 bits. In a long-pauses-between-updates scheme, this would generate a whole one-sample-period delay. Unfortunately this creates the requirement for a hardware-controlled NCS signal fed into !SYNC.
- The datasheet does not clarify whether or not extra clock pulses beyond 24 SCLK falling edges will be ignored, or whether the !SYNC rising edge latches the 24 most recent bits. My guess is that !SYNC falling edge resets a bit counter that counts to 24 to detect whether all bits have been transferred. The same compare match can then be used to disallow further shifts.
- DACx050x could conceivably be subjected to 32 bit transfers, so the device behavior is of interest. STM32G4 SPI DR width is 16 bit, so instead of writing three 8-bit words, it's possible to write two 16-bit words within the constraints of its 32-bit TX FIFO. This at least constructs a practical case where one would like to violate a strict 24 bit frame format if it offers any marginal performance benefit at all.

You may also come across this timing diagram that shows SCLK starting low at !SYNC falling edge, and is in agreement with the successful implementation described herein.


As far as timing minutiae, most intervals are tight (e.g. NCS: 13 ns setup and 10 ns hold), except for
- \> 160 ns of !SYNC inactive time between transfers
- \> 1000 ns wait time between DAC updates (t\_dacwait is not explained elsewhere, but "Update" is, suggesting that !SYNC rising edge after a valid transfer writing to BROADCAST or DACn-DATA is a singular event and the 1000 ns include the SPI transfer)


The DAC analog circuitry is much slower than that, taking a few microseconds under worst-case conditions to arrive at the new setpoint.

Do not expect to achieve the full 50 MHz baud rate, especially due to SCLK waveform challenges.

### Voltage Levels

For a device that needs up to 5.5V for normal operation and full output swing up to 5.0V, the lack of a separate VDDIO pin is interesting:

- VIL = 0.45V, VIH = 1.62V across the supply voltage range of 2.7V - 5.5V.
- capacitive loading causes SCLK skew and a DC offset, lowered amplitude. It seems that beyond 20 MHz, this is sufficient to keep the interface from working.
- An additional 1kOhm pull-down resistor on a 3.3V SCLK output can help extend operation to 32 MHz and perhaps beyond.
- Maybe experiment with hatched copper pour regions underneath the SCLK and MOSI traces to shave off 0.5-1 pF/cm of trace length. Do not exceed a few cm length as long as the 5th or 7th harmonic of SCLK does not spatially resolve the hatch pattern.

See https://baltic-lab.com/2023/08/critical-length-of-a-pcb-trace-and-when-to-treat-it-as-a-transmission-line/ for more:


- Some recommendations for 22- 330 Ohm series termination resistors apply. These are placed into all three SPI lines to attenuate reflections and to reduce the slew rate, which is beneficial for reduced feed-though to the output, but a trade-off when it comes to maximum throughput. But then again, a 32 MHz noise component on a few-100-kHz output is easy enough to filter or ignore. Recommendation. always place 0402 or 0603 resistors or (or CAY16 series arrays for that matter) in your design and mount zero Ohm resistors before eliminating them in the next revision if found to be unncessary.

## VREF settings and "No Output"

Diagnosing a new DACX0502 setup is complicated by the fact that in SPI mode, registers cannot be read and outputs staying at zero can be one of the following problems:
- SCLK too fast or signal integrity issue
- Wrong SPI mode or inadequate transfer timing
- REFDIV configuration not supported at the given supply voltage level (VDD).

Surely a 3.3V supply is sufficient for operation that does not exceed 2.5V? Indeed, the VREFIO bypass capacitor can be measured and there will be ~2.50V present, but this is not an indicator that the device will work as intended.

If it is what I think it is, then "REF-ALARM" is a misnomer. Note at first it says "betweeen reference and supply pins", perhaps to genealize and include external references:


But under GAIN, the alarm condition relates to the "DAC operating reference voltage":


Now there are 3 or 4 different things that could be called a reference voltage:
- the internal reference voltage output on VREFIO when it's in use
- an externally provided reference voltage
- the voltage after the reference divider controlled by REF-DIV
- the voltage provided to the R-2R block by the internal buffer


It's reasonable now to assume that "DAC operating reference voltage" means the internal buffer output to the R-2R block, and that buffer does not seem to be a rail-to-rail output (RRO) unity gain amplifier. At 3.3V, producing 2.5V would mean 800 mV headroom to VDD, and that's probably where the bottleneck is.

Searching for exact words in the datasheet often doesn't take one to the corresponding sections, such is the case for "analog threshold" and "threshold". Hunting for "REF-DIV" in turn brings up the basic requirement that for GAIN=1 (2x), the output shall not exceed VDD, though particular GAIN settings are not mentioned:


REF-DIV=0,GAIN=0 and REF-DIV=1,GAIN=1 should be synonymous, but intuition would lead one to prefer to reduce the amount of dividing and scaling of voltages to reduce errors. Does this hold?

Under Electrical Characteristics, a 0..2.5V range is realized through REF-DIV=1,GAIN=1 only:


But eventually, the REF-DIV=0,GAIN=0 combination shows up in Typical Characteristics curves:


There it is, the "minimum analog threshold": supplying 2.5V to the R-2R core becomes possible once the buffer following the reference divider block is supplied with 3.9V.

At that point, input and output voltages (each 2.50V) are 1400mV away from VDD.

> [!Warning]
> The REF-DIV=0,GAIN=0 combination will only work when VDD > 3.9V.
> Below 3.9V, the channels will output 0V.

## Conclusions

To establish basic functionality:

- Where possible operate DACX0502 at VDD=5V, VREFIO=2.5V (int. or ext. reference) REF-DIV=0,GAIN=0
- When operating at VDD=3.3V, REF-DIV=0,GAIN=0 will result in 0V output.
- When operating DACX0502 at VDD=3.3V, a 0 .. 2.5V range is only achieved by setting REF-DIV=1,GAIN=1. This will slightly degrade some of the specs, like Zero-Code Error.
- I2C is very slow compared to SPI, but 3-wire SPI will only allow writing to the DAC (SPI R/!W must be 0).
- SCLK, SDIN input levels are roughly compatible with LVCMOS25 voltage levels, only expecting a a lower VIL of 0.45V. There is no situation where the DAC would drive SDIN with 5V, so increasing DAC VDD is safe.

To help development and improve performance:
- When targeting 1-/ 2-channel devices and SPI, throw in and connect a DAC80504 footprint in parallel. Bring up the code being able to read back registers thanks to its 4-wire SPI.
- Have series resistors near the SPI pins on the master side (start with 22 Ohm, optionally fit 47 .. 100 Ohm resistors). These are series termination resistors to attenuate reflections of transients that got returned from the open-circuit side (the DAC).
- Series termination resistors double as test pads, but make sure to have a GND test pad nearby as well.
- Add a 1 kOhm pull-down resistor to the SCLK line. Above 15 MHz, microcontroller GPIO drive strength may be insufficient to provide adequate low level phases. This has been found in one case to extend the operating regime from an SCLK limit of 20 MHz to 32+ MHz.
- On PCBs with 4+ layers, consider using a hatched ground plane under the SPI traces to address the ~1pF/cm capacitive loading.