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title: VHDL Lab 6 Task

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## VHDL Lab 6 Task
In this task, you should create a similar clock as we've done in the recorded lab, but this clock should have two extra inputs:
1. `Increment Minutes` : This should increments the minutes every second when = '1'
2. `Increment Hours` : This should increments the hour every second when = '1'

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# VHDL Lab 6 Task
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