---
# System prepended metadata

title: VHDL LAB 7 Notes

---

# VHDL LAB 7 Notes

#### Algorithm:
```javascript=
function divide_unsigned (n, d) {
    q = 0;
    r = n;
    while (r >= d) {
        q = q + 1;
        r = r - d;
    }
    return [q, r];
}
```

#### Operations:

- RT Opertions with the q:
    - q <= q (idel)
    - q <= 0 (load)
    - q <= q + 1 (op)
- RT Opertions with the r:
    - r <= r (idel)
    - r <= n_in (load)
    - r <= r - d (op)
- RT Opertaions with the d:
    - d <= d (idel)
    - d <= d_in (load)
    - d <= d (op)

#### ASMD Chart:

<center>

![Sequential Division ASMD Chart](https://i.imgur.com/uObNgrV.png =300x)

Sequential Division ASMD Chart
</center>


