# VHDL LAB 7 Notes

#### Algorithm:

function divide_unsigned (n, d) {
    q = 0;
    r = n;
    while (r >= d) {
        q = q + 1;
        r = r - d;
    }
    return [q, r];
}

#### Operations:

- RT Opertions with the q:
- q <= q (idel)
- q <= 0 (load)
- q <= q + 1 (op)
- RT Opertions with the r:
- r <= r (idel)
- r <= n_in (load)
- r <= r - d (op)
- RT Opertaions with the d:
- d <= d (idel)
- d <= d_in (load)
- d <= d (op)

#### ASMD Chart:

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Sequential Division ASMD Chart
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