microcontroller lab
題目
連結可能失效!!!
; PIC18F4520 Configuration Bit Settings
; Assembly source line config statements
#include "p18f4520.inc"
; CONFIG1H
CONFIG OSC = INTIO67 ; Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOREN = ON ; Brown-out Reset Enable bits (Brown-out Reset enabled and controlled by software (SBOREN is enabled))
CONFIG BORV = 3 ; Brown Out Reset Voltage bits (Minimum setting)
; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = PORTC ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)
org 0x00
goto init
DELAY macro num_out, num_in
local outerloop
local innerloop
movff WREG, 0x04
movlw num_out
movwf 0x14
outerloop:
movlw num_in
movwf 0x03
innerloop:
nop
nop
nop
nop
nop
nop
nop
nop
nop
decfsz 0x03, 1, 0
bra innerloop
decfsz 0x14, 1, 0
bra outerloop
movff 0x04, WREG
endm
init:
movlw d'60'
movwf LATD
clrf TRISB
clrf PORTB
clrf LATB
bsf TRISB, 0
clrf TRISC
clrf LATC
;set RB0 to digital input
clrf ADCON1
bsf ADCON1, PCFG2
;set clock to 125kHz
bcf OSCCON, IRCF2
bcf OSCCON, IRCF1
bsf OSCCON, IRCF0
;set PR2 to 156
movlw d'155'
movwf PR2
;set CCP1 to PWM & set P1A to single output
;bsf CCP1CON, P1M1
;bsf CCP1CON, P1M0
bsf CCP1CON, CCP1M3
bsf CCP1CON, CCP1M2
bcf CCP1CON, CCP1M1
bcf CCP1CON, CCP1M0
;set duty cycle to 500us
bcf CCP1CON, DC1B1
bcf CCP1CON, DC1B0
movlw b'00000100'
movwf CCPR1L
;turn on TMR2 & set pre-scaler to 4
bcf T2CON, T2CKPS1
bsf T2CON, T2CKPS0
bsf T2CON, TMR2ON
start:
btfsc PORTB, 0
rcall move
goto start
move:
rcall add
DELAY 0x0A, 0x0A
decf LATD
btfss STATUS, Z
goto move
movlw b'0000100'
movwf CCPR1L
bcf CCP1CON, DC1B0
bcf CCP1CON, DC1B0
DELAY d'50', d'20'
movlw d'60'
movwf LATD
return
add:
btfsc CCP1CON, DC1B0
rcall add2
btg CCP1CON, DC1B0
return
add2:
btfsc CCP1CON, DC1B1
incf CCPR1L
btg CCP1CON, DC1B1
return
end
or
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