---
# System prepended metadata

title: Computer Architecture Hw3
tags: [Computer Architecture]

---

# Computer Architecture Hw3
###### tags: `Computer Architecture`
<pre class="tab"><b>姓名：林宗佑,      學號：10967130       題號：3, 6</b></pre>
## 題3:Exercise C.6 a b c d
**Ans:** 
### a. 
Triditional 5-stage RISC implementation is IF->ID->EX->MEM->WB.  This order is suitable for register-register operation due to the registers needed in EX stage are all accessed in ID stage which is before EX stage.
For Register memory operation, register and memory needed in EX stage should be accessed before EX stage. We should exchage the position of EX stage and MEM stage.
*++Rearranged order of RISC stages: IF->ID->MEM->EX->WB++*


### b. 
There are three kinds of forwarding for the rearranged implementation of RISC mentioned in 3a:
#### 1. MEM stage -> MEM stage:
usage example: 
1. load R1, (X1)
2. store R1, (X2)
#### 2. EX stage -> MEM stage:
usage example: When a EX stage caculate the memory address needed in the following load store instruction. This forwarding can prevent pipeline from stalled. 

#### 3. EX stage -> EX stage:
usage example:
1. add x2, x3, (x1)
2. sub x4, x2, (x1)

*++New forwarding path: MEM->MEM, EX->MEM, EX->EX++*

### c.
The following lists the possible data hazard:
1. Load Store address caculated by previous ALU operation 
    ex: 
    > ADD R1, R2, (X1)
    > LD  R3, (R1)
2. Store instruction with register data caculated by previous ALU operation
    ex:
    > ADD R1, R2, (X1)
    > SW (R3), R1

### d.
Original pipeline stage order: IF->ID->EX->MEM->WB
New pipeline stage order: IF->ID->MEM->EX->WB
|Original pipeline |New pipeline|instruction count variation|
|-----|--------|--------|
|Load R2, 100(R1)|ADDUI R3, R1, #100 <br> LD R2, R3 |increase
|ADD R1, R2, R3 |ADD R1, R2, (R3) | no change
|Load R4, (R3) <br> ADD R1, R2, R4|ADD R1, R2, (R3) |decrease


## 題6:Exercise 3.15 a
Ans: The loop in 3.14 is as the image bellow:
![](https://i.imgur.com/YCCa2pM.png)
***
Due to the assumption 3:" The execution stage (EX) does both the effective address calculation and the memory access for loads and stores. Thus, the pipeline is IF/ID/IS/EX/WB.", I combined Execute stage and memory access stage together.
Thus, the headers of the columns in the answer table should be: iteragion, instruction, issue at, Execute/MEM, Write CBD.

The Answer sheet is shown bellow:

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