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# System prepended metadata

title: Homework5

---

# Homework5
> 資工二1 黃柏芸
> 指導老師：林宏益
 
### 實驗目的:
請設計Pseudo Random Pattern Generator具有同步正準位設定的功能，當設定時，輸出為1102 ，並撰寫testbench,產生僞隨機數的方法最常見的是利用一種線性反饋移位寄存器(LFSR)
1) Design a Pseudo Random Pattern Generator
1.1) A linear feedback shift Register (LFSR)
1.2) Feedback equation X3＋X＋1
1.3) Random sequence 1、3、7、6、5、2、4 、1……( without 0)
1.4) For N stage, LFSR can generate 2N-1 sequence ( i.e., 1~ 2N-1)
2) This LFSR with positive Synchronous set, when the set is activate,
the output of LFSR is (110)2
### 程式碼:

>design部分
```verilog=
`timescale 1ns / 100ps
module LFSR #(parameter NUM_BITS=3)
  (
   input i_Clk,
   input i_Enable,

   input i_Seed_DV,
    input [32:0] i_Seed_Data,

    output [32:0] o_LFSR_Data,
   output o_LFSR_Done
   );

  reg [32:1] r_LFSR = 0;
  reg              r_XNOR;

  always @(posedge i_Clk)
    begin
      if (i_Enable == 1'b1)
        begin
          if (i_Seed_DV == 1'b1)
            r_LFSR <= i_Seed_Data;
          else
            r_LFSR <= {r_LFSR[NUM_BITS-1:1], r_XNOR};
        end
    end
  
  always @(*)
    begin
      case (NUM_BITS)
        3: begin
          r_XNOR = r_LFSR[3] ^~ r_LFSR[2];
        end
        4: begin
          r_XNOR = r_LFSR[4] ^~ r_LFSR[3];
        end
        5: begin
          r_XNOR = r_LFSR[4] ^~ r_LFSR[3];
        end
        6: begin
          r_XNOR = r_LFSR[6] ^~ r_LFSR[5];
        end
        7: begin
          r_XNOR = r_LFSR[7] ^~ r_LFSR[6];
        end
        8: begin
          r_XNOR = r_LFSR[8] ^~ r_LFSR[6] ^~ r_LFSR[5] ^~ r_LFSR[4];
        end
        9: begin
          r_XNOR = r_LFSR[9] ^~ r_LFSR[5];
        end
        10: begin
          r_XNOR = r_LFSR[10] ^~ r_LFSR[7];
        end
        11: begin
          r_XNOR = r_LFSR[11] ^~ r_LFSR[9];
        end
        12: begin
          r_XNOR = r_LFSR[12] ^~ r_LFSR[6] ^~ r_LFSR[4] ^~ r_LFSR[1];
        end
        13: begin
          r_XNOR = r_LFSR[13] ^~ r_LFSR[4] ^~ r_LFSR[3] ^~ r_LFSR[1];
        end
        14: begin
          r_XNOR = r_LFSR[14] ^~ r_LFSR[5] ^~ r_LFSR[3] ^~ r_LFSR[1];
        end
        15: begin
          r_XNOR = r_LFSR[15] ^~ r_LFSR[14];
        end
        16: begin
          r_XNOR = r_LFSR[16] ^~ r_LFSR[15] ^~ r_LFSR[13] ^~ r_LFSR[4];
          end
        17: begin
          r_XNOR = r_LFSR[17] ^~ r_LFSR[14];
        end
        18: begin
          r_XNOR = r_LFSR[18] ^~ r_LFSR[11];
        end
        19: begin
          r_XNOR = r_LFSR[19] ^~ r_LFSR[6] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end
        20: begin
          r_XNOR = r_LFSR[20] ^~ r_LFSR[17];
        end
        21: begin
          r_XNOR = r_LFSR[21] ^~ r_LFSR[19];
        end
        22: begin
          r_XNOR = r_LFSR[22] ^~ r_LFSR[21];
        end
        23: begin
          r_XNOR = r_LFSR[23] ^~ r_LFSR[18];
        end
        24: begin
          r_XNOR = r_LFSR[24] ^~ r_LFSR[23] ^~ r_LFSR[22] ^~ r_LFSR[17];
        end
        25: begin
          r_XNOR = r_LFSR[25] ^~ r_LFSR[22];
        end
        26: begin
          r_XNOR = r_LFSR[26] ^~ r_LFSR[6] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end
        27: begin
          r_XNOR = r_LFSR[27] ^~ r_LFSR[5] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end
        28: begin
          r_XNOR = r_LFSR[28] ^~ r_LFSR[25];
        end
        29: begin
          r_XNOR = r_LFSR[29] ^~ r_LFSR[27];
        end
        30: begin
          r_XNOR = r_LFSR[30] ^~ r_LFSR[6] ^~ r_LFSR[4] ^~ r_LFSR[1];
        end
        31: begin
          r_XNOR = r_LFSR[31] ^~ r_LFSR[28];
        end
        32: begin
          r_XNOR = r_LFSR[32] ^~ r_LFSR[22] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end

      endcase 
    end 

  assign o_LFSR_Data = r_LFSR[NUM_BITS:1];
  assign o_LFSR_Done = (r_LFSR[NUM_BITS:1] == i_Seed_Data) ? 1'b1 : 1'b0;

endmodule
```

>test bench部分
```verilog=
`timescale 1ns / 100ps

`define N_BITS 4
module tb_lfsr;
	reg i_Clk;
	reg i_Enable;
	reg i_Seed_DV;
  reg [32:0] i_Seed_Data;
  wire [32:0] o_LFSR_Data;
	wire o_LFSR_Done;
	LFSR #(.NUM_BITS(`N_BITS)) dut(
            .i_Clk(i_Clk),
            .i_Enable(i_Enable),
            .i_Seed_DV(i_Seed_DV),
            .i_Seed_Data(i_Seed_Data),
            .o_LFSR_Data(o_LFSR_Data),
            .o_LFSR_Done(o_LFSR_Done));
	
	always #10 i_Clk = ~i_Clk;
	
	initial begin
		i_Clk = 0;
		i_Enable = 0;
		i_Seed_DV = 0;
		i_Seed_Data = 0;
		
		#15;
		i_Enable = 1;
		i_Seed_DV = 1;
		@(posedge i_Clk);
		#5;
		i_Seed_DV = 0;
	end
	
endmodule
```
### 分析:
n個D觸發器最多可以提供2^n-1個狀態(不包括全0的狀態):所以3個D觸發器會有1、3、7、6、5、2、4 不段循環的7種狀態

### 心得:
因為Pseudo Random Pattern Generator是我第一次聽到、接觸到的東西，所以在網路上找了很多資料，且理解程式是一回事，實現出來又是一回事了，我得更加努力才行!

### github連結:
https://gist.github.com/BoyunHuang/fd4d8239120945d0e35dae1fdcaa1ccb
