---
# System prepended metadata

title: 'Regular MPW Meeting Logs - June 8th, 2021'
tags: ['Tag(Keio team, Quanray team)']

---

# Regular MPW Meeting Logs - June 8th, 2021

###### tags: `Tag(Keio team, Quanray team)`

| Features        |   Data                  |
| ----------------|:----------------------- |
| Project:        | MSMA LSI Tag Development|
| Facilitator:    | Jin Mitsugi, Hao Min    |
| Date:           | June 8th, 2021          |
| Time:           | 13:30-14:30 Beijing Time|
| Attendees:      | Hao Min, Jin Mitsugi, Jiabin Zhou, Qingsong Zhang, Yongming Xu, Yuxiao Zhao, H. Takahashi, Yichao Zhang, Yu Lu, Vrishti Shersia        |
| Logger:         | Vrishti Shersia         |

## :memo: Logs
## Action Item Updates 
* [cont] Quanray will provide a detailed simulation model and FPGA implementation for the Duplex method: Quanray to send the advancement report due on June 8th->open
* [cont] Modified FPC Design and Delivery: FPC is under fabrication now->open.
* [new] Quanray to fabricate 150 MSMA chips in the E-garde project (50 for metal antenna, 50 for battery assisted tag in the second half of 2021. And spare 50):Different contract->closed 
* [cont] Battery-Assisted mode examination: A good combination of commercial voltage booster and Jupiter1 chip are still in pipeline according to Keio->open 
* [cont] Requirements to the new RFIC shall be clarified (Keio): View the updated Jupiter 2 spec. https://msma-prj.autoidlab.jp/attachments/394: GPIO discussion=>can be done. Quanray will check the spec->open
* [cont] Quanray to buy and implement die of ADXL-362 from ADI to implement into the package: Keio recommends Quanray to give the chip to ADI for implementation and design the chip for the MEMS circuitry->closed. As follow up. Keio had a meeting with ADI sales. They said it is very difficult to provide bare chip because of the package is essential to produce the performance written in the specification. However, they said it might be possible to put jupyter2 RFIC into their package. 
* [new] eqRN before WRITE: Major portion of subcarrier allocation using DCO_CTL is consumed by the collection of new RN16 every time a DCO_CTL value is written. Keio inquires if it is possible to reuse a handle for repetitive writes, or reduce the number of Req_RN, eg., once in three WRITE commands?:Quanray to check with Engineer->open 
* [cont] The process of contract through Toppan to be initiated in May->open
* [cont] Production and Delivery of Type-A PCBs(20): (refer Minutes of April 28th)->open 
* [new] Quanray to produce the explanation on ADC resolution and SNR (eNob)->open

## Conclusions: 

* Duplex simulation: Quanray has finished Behavior level simulation and is working on circuit level simulation. 10k subcarrier shows promising result to produce stable clock. With 2.5kbps forward link, Full duplex should be fine. Dynamic range of near-far problem exists due to the distance. 10Hz Sync command instead of continuous subcarrier to be used with 100 msec interval. 
* FPC delivery: Scheduled delivery of 3-FPCs with ADXL & cap and 7-FPCs without ADXL & cap will be done by Quanray till 18th June.
* RFIC Spec: Keio has provided a document, experimenting on skipping Req_RN before WRITE to speed up DCO allocation. If we skip the redundant Req_RN, we can speed up the initial channel allocation. Further, Quanray to check the protocol command.
* Architecture of ADC: Quanray to provide tradeoff between the resolution and SNR. We need to limit the bandwidth to 250Hz from 500Hz. By reducing the sampling rate, we can achieve 16 bit resolution. Quanray will find out whether QST Accelerometer will work or not. 
* Toppan Contract: Quanray sent quote of the development. The specification of the deliverables needs to be discussed. They will send spare tags by the end of this fiscal year. 


## Next Meeting:

* On June 22nd, 2021 at 13:30-14:30 Beijing Time.

## Technical Conversations:

* Quanray has simulated 10K subcarrier with no issue, behaviour level simulation is done. 10k subcarrier is issued from Reader Writer. They are working on the circuit level simulation to produce stable clock. Oscillator will check the 10K subcarrier which is very accurate. Phase locked loop is in the subcarrier. The chip needs to be demodulated while sending backscatter. Separate the subcarrier and clock filter to filter out backscatter. Subcarrier from tag to Reader Writer is not constantly continuous. This leads to jitter production. Special Sample and hold circuit is implemented. After filtering, the clock and data are recovered at the same time. 

* In case of Full Duplex: With 10% Modulation Index, checking the dynamic range, some tags are close and some are far. 10db>Input>-14db with 25db dynamic range. If continuous subcarrier can't be sent, talking command to be sent at 100msec. We calibrate the clock frequency and demodulate the command between the two downlink talking command. Tracking of the oscillator takes place. Time interval is long compared to the oscillator. Circuit structure could be changed. The issue is we see ripples of frequency<0.1%. PLL reference clock is very long. The DCO is adjusted, when Sync command is received. Vibration in DCO may lead to discrepancy. With longer interval, clock is unstable. Time interval of 100msec is feasible. No. of counters could be increased. Sending talking command continuously is equivalent to 50Hz, i.e. every second send 50 times with bit rate 2.5kbps. Interval of Sync signal, from 10Hz to 1Hz is 20% duty cycle. 

* RFIC spec: Keio is looking into charging the battery to save battery. If fading occurs, sensor stops working, GPIO control, command from the chip. Regarding DCO control, besides the tracking control, subcarrier is sent to a particular tag. Because of Gen2 requirement, the tag will go to inactive mode. If Req_RN is not sent, the tag is in open state. The handler will change. RN_16 is to secure the data anti-collision. After inventory tag, tag comes to open state. Req_RN updates RN_16. RN_16 is used to encrypt the data. Quanray will check the protocol command. Before write command, Reader Writer needs to send the Req_RN. The machine will wait for the Req_RN. Executive consecutive writing. Authentication and authorization of tags. It will tremendously speed up the DCO controller. 

* Architecture of ADC: 4 channel ADC in the chip tag. 1 ADC port is available. Function of the multiplexer is to send one at a time. In the Multicontroller unit, external ADC we have one channel. Inside, the sensor we have 4 channel ADC. Input can be selected 1/2/4 channel. 500Hz BandWidth is equivalent to Nyquist frequency, Maximum sampling rate of 1kHZ. Noise shaping SAR(new ADC structure): SAR ADC + Sigma DELTA ADC. And 'L' is the order of the noise shaping filter. Theoretically, we can get 16 bit. Relationship between sampling frequency and resolution is 1k->8 bit, 2k->9bit, 64k->8+6->14bit. If we increase the resolution from 14 to 16 bit, the SNR gets sacrificed. It will worsen the SNR as low SNR is detrimental for our measurement. When resolution is 16bit, Equivalent no. of bits(eNob) can't be guaranteed to 16 bit. eNob is proportional and is lower than resolution. Issue of noise shaping is integrated non-linearity and differential non-linearity. If LPF is applied, higher SNR could be achieved. 