---
# System prepended metadata

title: 'MPW LSI Meeting Logs - June 22nd, 2021'
tags: ['Tag(Keio team, Quanray team)']

---

# MPW LSI Meeting Logs - June 22nd, 2021

###### tags: `Tag(Keio team, Quanray team)`

| Features        |   Data                  |
| ----------------|:----------------------- |
| Project:        | MSMA LSI Tag Development|
| Facilitator:    | Jin Mitsugi, Hao Min    |
| Date:           | June 22nd, 2021         |
| Time:           | 13:30-14:30 Beijing Time|
| Attendees:      | Hao Min, Jin Mitsugi, Yuxiao Zhao, H. Takahashi, Yichao Zhang, Yu Lu, Vrishti Shersia|
| Meeting Link    | https://keio-univ.zoom.us/j/86364000729?pwd=ZVNmZ2dOT3JZUWtpRlkyQmt0QUVIQT09        |
| Logger:         | Vrishti Shersia         |

## :memo: Logs
## Action Item Updates 
* [cont] Quanray will provide a detailed simulation model and FPGA implementation for the Duplex method: Quanray to send the advancement report-> shared before the next meeting on July 6th. 

* [cont] Modified FPC Design and Delivery: FPC is under fabrication now->open
-> Kuanfeng sent the FPC and Type-A to Japan on delivery now. 
* [cont] Battery-Assisted mode examination: A good combination of commercial voltage booster and Jupiter1 chip are still in pipeline according to Keio->report in the next meeting. 
* [cont] Requirements to the new RFIC shall be clarified (Keio): Keio rewrote the specification as a whole set. View the updated Jupiter 2 spec. https://msma-prj.autoidlab.jp/attachments/416 -> close for now
* [cont] Quanray to buy and implement die of ADXL-362 from ADI to implement into the package: As a follow up, Keio had a meeting with ADI Japan sales. They said it is very difficult to provide bare chips because the package is essential to produce the performance written in the specification. However, they said it might be possible to put Jupiter2 RFIC into their package->closed
* [cont] eqRN before WRITE: Major portion of subcarrier allocation using DCO_CTL is consumed by the collection of new RN16 every time a DCO_CTL value is written. Keio inquires if it is possible to reuse a handle for repetitive writes, or reduce the number of Req_RN, eg., once in three WRITE commands?-> We can have this option but not do this to keep the Gen2 compatibility. ->closed 
* [cont] Updates regarding the Toppan contract : Quanray sent quote of the development. The specification of the deliverables needs to be discussed->Toppan issued a quote to Keio, we start the paper work. 
* [cont] Production and Delivery of 
    * Type-A PCBs(20) -> on delivery now
    * RFIC (300)
    * RFIC for Arizon Japan Antenna for 2021(150) 
    * RFIC for Toppan(enclosed in a tray)(50) ->open
* [new] Quanray to produce the explanation on ADC resolution and SNR (eNob-equivalent number of bit)->16 bits resolution with 1kbps.-> close

## Conclusions: 

* Duplex method: Quanray to review the simulation reports and share with Keio by the end of June.
 
* 10 FPC: Scheduled delivery of 3-FPCs with ADXL & cap and 7-FPCs without ADXL & cap will be done by Quanray.
* Quanray checked with the QR engineer about the RN16 issue. Keio thinks the compatibility with Gen2 protocol should be kept intact, as Quanray suggested. The Req_RN skip option to be disregarded. Keio agrees to go with the GEN2 conformal design(No change in Gen2 protocol). 
* Progress on Toppan: Quote has already been confirmed with Quanray. Discussion about the deliverables is ongoing. Keio will talk to Toppan to initiate contract with Keio and provide their quote.
* Production and delivery of Type A PCB: Type A PCBs have been sent for SMT soldering. 
* Quanray to provide 300 RFIC bare chips and 150 RFICs for Arizon Japan. Toppan wants to do the wirebonding by themselves and require 50 RFIC chips. It consists of plastic case with die in it. Keio would reissue a document for handling. 
* Prototype requirement: Many academic people are working using the inventory. They apply backscatter and measure the vibration. The constant timeline interval is not there. By using subcarrier with Gen2 command with a software defined Reader they can produce a subcarrier. A prototype is required for the research community concerning about 100 dies for this purpose.
* Internal specification of oversampling ADC: We measure the performance and resolution of ADC. In Equivalent ADC, 1 bit is 6.02 db SNR. Equivalent no. of bits, signal noise is equivalent to number of bits. For 1 channel->18 bits. Other noises conservatively we say 14 bits. No. of bits captured from ADC is about 16 bits(target). 64 times higher than 1k sampling rate. If we double the sampling rate, atleast we can get 6 extra bits compared to original ADC. 6x1.5=9 bit extra. About 8+9=17 to 18 bits.


## Next Meeting:

* On July 6th, 2021 at 13:30-14:30 Beijing Time.

## Technical Conversations:
 
* Keio compiled the Jupiter 2 specification as a complete set. DCO register number has an issue: 14 bits which is not monotonic. Non-linearity of DCO is larger than the DCO. We require better regulation from the DCO for the linearity. Automatic tracking needs monotonocity. If it's not monotonic then it will not be stable. 

* ADC is allowed to have 14 bits. Data format is in 16 bits. Increase the bandwidth, we need tradeoff between number of bits and SNR. ADC is called oversampling ADC. For normal ADC, differential and non-differential linearity is considered. For oversampling ADC, we use SNR. 
* It depends on oversampling ratio, for higher resolution with lower sampling rate we get extra 1 and 1/2 bits. Reader/Writer parameter, 1k sample/sec. Destination filter will filter out noise and we can have higher resolution. Reduce sampling rate by 1/2, noise gets half. This is the tradeoff. Quantization noise has gaussian distribution. If noise is gaussian it is evenly distributed in the system. LPF will filter out the quantization noise. This is how non-oversampling ADC works. Reduce sampling rate on application side and increase resolution. This decimation is done in Reader. Instruct the chip to change the sampling rate would require extra circuitry to configure sampling rate. 1 ADC port is present. Sampling frequency is fixed. Temperature sensor inside RFIC. If we instruct RFIC to append the temperature data to the end of the SPI sensor capture data. ADXL is allowed. Configure temperature sensor and external analog input. ADC is connected to RFIC through SPI. ADC is inside the sensor chip. We may have external SPI sensor, temperature measurement can be combined with ADC sensor measurement. SPI is interfaceable. Configure either J2 sensor or ADXL-362, DCO-Lock command. Bare chip ADXL in the package. We have SPI bus for the external SPI sensor. 