# Minutes of Meeting - April 28th, 2021

###### tags: `Tag(Keio team, Quanray team)`

| Features | Data |
| ----------------|:----------------------- |
| Project: | MSMA LSI Tag Development|
| Facilitator: | Jin Mitsugi, Hao Min |
| Date: | April 28th, 2021 |
| Time: | 13:30-14:30 Beijing Time|
| Attendees: | Hao Min, Jin Mitsugi, Yuxiao Zhao, Vrishti Shersia |
| Logger: | Vrishti Shersia |

## :memo: Logs
## Action Items updates
* [close] Sensor G-range and power consumption estimate shall be provided (Quanray): Provided on April 20th->closed QST sensor is no longer on Jupter2.
* [new] Quanray's Plan to develop the Duplex mechanism due on April 28th: Simulation and design are going on in Quanray->open
* [cont] Modified FPC Design and Delivery: Quanray has got the new design and will arrange the manufacturing->open
* [cont] Reason behind the Discontinuous frequency characteristics in Type C and Type D CoB->open
* [cont] Battery-Assisted mode examination: Keio will check another tags->open
* [cont] Requirements to the new RFIC shall be clarified (Keio): The updated Jupiter 2 spec. https://msma-prj.autoidlab.jp/attachments/394 ->open
* [new] The process of contract through Toppan to be initiated in May->open
* [new] Production and Delivery of Type-A PCBs(20)->open

## Conclusions:
* QST accelerometer won't be used in Jupiter2
* Analog sensor shall be supported by Jupiter2 with 4ksps with 16bits. Quanray to check the possibility.
* Quanray to provide proposal on
* Block diagram of the chip
* Specification of STRM(Sync) subcarrier specification.
* Specification of head of preamble STRM(Stop) command (downlink).
* Voltage booster implementation.
* Quanray to try to buy and implement die of ADXL362 from ADI to implement into the package: Keio recommends Quanray to give the chip to ADI for implementation. We have RFIC with the sensor. SAR is implemented in the QST sensor. Design the chip for the MEMS circuitry.
* Output voltage from energy harvesting: Quanray conclude that the maximum output voltage of current chip is still 2.0V. If higher voltage is required, external voltage booster could be used.
* Type-A is very convenient for testing. Keio requires demo of Type-C.
* Implementation of FPGA in July/August. Delivery of the first version of the chip has been extended by 2 months from Dec'21. It is expected by Feb.

## Next Meeting:

* May 11th, 2021 13:30-14:30 Beijing Time.

## Technical Conversations:

* The ADI chip we are using is high performance chip worldwide. The Embedded sensor has low power and hence QST performance is not good as compared with ADI sensor. From the power consumption point of view ADI sensor is good. QST chip can't go higher ADC range.

* Proposed changes and new functions to Gen2 Communication protocol and Jupiter 2 RFIC:
* Quanray's proposal to implement the Stream(Stop) and Stream(Sync). After sending the Stream(START), the reader start to send continuous subcarrier= 5kHz. The downlink command with a frame structure and modulate the 5k subcarrier at 5Kbps. Quanray will propose a new leading bits which violate PIE encoding, SPI Read.

* CPOL(clock polarity) is for CS.
* RFIC can be sustained with instantaneous power down caused by fading: Quanray proposed to use a Super Cap.
* RFIC power can be charged into an external rechargeable battery with an external voltage booster: Currently, the maximum output voltage of the energy harvest is 2~2.2V. Stability is 5%, easier to achieve when backscattered, duration is very short. Super Cap to be placed outside the chip. Inorder to charge solid state battery 2.7V, better to have voltage outside the chip. We will O/P 2.6V. Transistor should be high voltage device. Difficult to put this voltage booster circuitry inside the RFIC. Possible to o/p the clock, external voltage booster coming from outside the RFIC.