# MPW LSI Meeting Logs - July 20th, 2021

###### tags: `Tag(Keio team, Quanray team)`

| Features | Data |
| ----------------|:----------------------- |
| Project: | MSMA LSI Tag Development|
| Facilitator: | Jin Mitsugi, Hao Min |
| Date: | July 20th, 2021 |
| Time: | 13:30-14:30 Beijing Time|
| Attendees: | Hao Min, Jin Mitsugi, Yuxiao Zhao, H. Takahashi, Yongming Xu, Yichao, Yu Lu, Jiabin Zhou, Mahiro Yakabe, Vrishti Shersia |
| Meeting Link | https://keio-univ.zoom.us/j/86364000729?pwd=ZVNmZ2dOT3JZUWtpRlkyQmt0QUVIQT09 |
| Logger: | Vrishti Shersia |

## :memo: Logs
## Action Item Updates
* [new] Quanray to send the ADFLL and demodulator documents to Keio->open
* [new] Durability of Jupiter2 under instantaneous power down caused by fading->open
* [new] Standardization in Gen2 modernization in GS1: Quanray will talk to China GS1 and ISO->open
* [new] Durability of Jupiter2 against temporal power down due to fading need to be discussed->open

## Conclusions:
* Setup a timeline for FPGA testing for Jupiter 2 protocol: By middle of August.
* Power suspension against the temporary fading needs to be talked through.

## Next Meeting:

* Aug 3rd, 2021 at 13:30-14:30 Beijing Time.

## Technical Conversations:

* Progress report is explained. The DCO adjustment while the tag backscatter works according to simulation both in subcarrier of 10kHz and token. The settling time is about 25msec.
* Simulation of clock recovery on duplex: Scheduling the FPGA port and simulating the FPGA plan in clock recovery. Clock recovery is different when FPGA is ready. Target is mid of August.
* Standardization in Gen2 modernization (new version of Gen2): Future version of Gen2 to be used in business requirement for new protocol sensor data streaming. They understand the necessity of streaming. Renewing ISO 180063. EM micro electronics proposing sensor, add special command to interface with the sensor. Accelerate the inventory, they will come up with streaming instead of snapshot. Quanray to approach GS1 and ISO in China. Keio showed video of the streaming. Try to have a Synchronous sensor reader. Time demux is used, hence no synchronous reading. Streaming will be better. EMP Board can come up with sensor streaming. Quanray is joining 3GPP standard body for 5G. MMPC for 5G NR(new radio) Advance Passive 5G IOT. Framework is based on 5G. Working on protocol, downlink, uplink, Network layer. Passive and semi-passive tags are in low bit rate. Very densely located base station, maximum interval between two 5G stations will be less than 200m. Communication range 100-200m. 5G link layer, sensor will be a 5G package. China mobile is supporting Quanray's initiative. Ambient backscatter with 6G. Originally proposed as 6G but moved 5.5G. Power consumption requirement is 100uW. Use energy harvest. Quanray has draft of the standard and demo would be available by the end of this year. Quanray to prepare a report on Power management of Jupiter 2.
* CRU design Report: Simulink ADFLL(ALL digit frequency locked loop) & Communication Module Sim. Simulation summary at simulink is when Reference frequency is 10K, lock time<25msec, then settling time is <25msec. Reference frequency is 20Hz(<100Hz), then settling time is <30msec.
* The Communication module and ADFLL have only one port connected so as long as comm module can demodulate the clock that meets the requirement i.e. ADFLL can normally realize USC tracking (DSC &Token pulse).
* Model Sim can't display the waveform, but result is closed to the simulink modeling result. Adjust the DCO clock when tag backscatters the Reader/writer. Tag needs to avoid Subcarrier interval.
* Subcarrier interaction to DCO tuning modeling: We need to do tuning while tag is backscattering. The interrogator tag to tune the DCO to the designated Subcarrier frequency. Tag is USC STW. When backscattering, overlap will cause jitter. Maximum jitter is 10usec, minimum backscatter frequency is 100k. Downlink Subcarrier can be extracted: When backscattering is happening in the demodulator, we put it on hold and when there is no backscatter, we put it on sample. DCO register is 14 bit + 2 overlap bits. DCO has 3 range: coarse, medium, fine. There is always one bit overlap.