# Asssigment3: SoftCPU

contributed by <`erickuo5124`>

###### tags: `Computer Architecture 2021`

Requirements:

1. Following the instructions of srv32 - RISCV RV32IM Soft CPU, you shall modify the assembly programs used/done with Assignment1 for srv32 Simulation with Verilator.
2. Check the generated file wave.fst and use GTKwave to view the waveform. Then, explain how your program is executed along with srv32 Simulation.
3. Propose the software optimizations (against your program) based on the pipeline design of srv32.
4. Write down your thoughts and progress in HackMD notes.

---

## Modify Assignment1 for srv32 Simulation with Verilator

### C code

#include <stdio.h>

int find_compl(int n)
{
    int mask = 0xffffffff;
    while (mask & n)
	mask <<= 1;
    return n ^ ~mask;
}

int main(void)
{
    int ipt = 1;
    int res = find_compl(ipt);

    printf("%d\n", res);
    return 0;
}

### Execution result

kuouu@uuASUS:~/srv32$ make hw3
make[1]: Entering directory '/home/kuouu/srv32/sw'
make -C common
make[2]: Entering directory '/home/kuouu/srv32/sw/common'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/kuouu/srv32/sw/common'
make[2]: Entering directory '/home/kuouu/srv32/sw/hw3'
riscv-none-embed-gcc -O3 -Wall -march=rv32im -mabi=ilp32 -nostartfiles -nostdlib -L../common -o hw3.elf main.c -lc -lm -lgcc -lsys -T ../common/default.ld -g
riscv-none-embed-objcopy -j .text -O binary hw3.elf imem.bin
riscv-none-embed-objcopy -j .data -O binary hw3.elf dmem.bin
riscv-none-embed-objcopy -O binary hw3.elf memory.bin
riscv-none-embed-objdump -d hw3.elf > hw3.dis
riscv-none-embed-readelf -a hw3.elf > hw3.symbol
make[2]: Leaving directory '/home/kuouu/srv32/sw/hw3'
make[1]: Leaving directory '/home/kuouu/srv32/sw'
make[1]: Entering directory '/home/kuouu/srv32/sim'
0

Excuting 1245 instructions, 1599 cycles, 1.284 CPI
Program terminate
- ../rtl/../testbench/testbench.v:418: Verilog $finish

Simulation statistics
=====================
Simulation time  : 0.019 s
Simulation cycles: 1610
Simulation speed : 0.0847368 MHz

make[1]: Leaving directory '/home/kuouu/srv32/sim'
make[1]: Entering directory '/home/kuouu/srv32/tools'
./rvsim --memsize 128 -l trace.log ../sw/hw3/hw3.elf
0

Excuting 1245 instructions, 1599 cycles, 1.284 CPI
Program terminate

Simulation statistics
=====================
Simulation time  : 0.001 s
Simulation cycles: 1599
Simulation speed : 2.558 MHz

make[1]: Leaving directory '/home/kuouu/srv32/tools'
Compare the trace between RTL and ISS simulator
=== Simulation passed ===

### Step

1. [Setup note](https://hackmd.io/@eecheng/B1fEgnQwF)
2. rewrite C code

## GTKwave waveform