---
# System prepended metadata

title: Lab 8

---

# Lab 8
Name: Sai Kowshik Allu
Roll No.: CS22B004

---
## Question 1
```verilog=
module fulladderh(sum,cout,a,b,c);
input a,b,c;
output sum,cout;
wire w1,w2,s;
halfadder1 h1(w1,w2,a,b);
halfadder1 h2(sum,s,w1,c);
assign cout = w2 | s;
endmodule
```
Testbench
```verilog
module fulladderh_testbench();
reg a1,b1,c1;
wire sum1,cout1;

fulladderh out(.a(a1),.b(b1),.c(c1),.sum(sum1),.cout(cout1));

initial 
begin
a1 = 0; b1 = 0; c1 = 0;
#100
a1 = 0; b1 = 0; c1 = 1;
#100
a1 = 0; b1 = 1; c1 = 0;
#100
a1 = 0; b1 = 1; c1 = 1;
#100
a1 = 1; b1 = 0; c1 = 0;
#100
a1 = 1; b1 = 0; c1 = 1;
#100
a1 = 1; b1 = 1; c1 = 0;
#100
a1 = 1; b1 = 1; c1 = 1;


end
endmodule

```
![fullwithhalf](https://hackmd.io/_uploads/SyMB-n1xR.jpg)






## Question 2
4bit adder code
```verilog=
module rca(
    input [3:0]a,b,
    input cin,
    output [3:0]sum,
    output c4);

wire c1,c2,c3;      //Carry out of each full adder

fulladderh fa0(a[0],b[0],cin,sum[0],c1);
fulladderh fa1(a[1],b[1],c1,sum[1],c2);
fulladderh fa2(a[2],b[2],c2,sum[2],c3);
fulladderh fa3(a[3],b[3],c3,sum[3],c4);
                
endmodule

```
testbench

```verilog=
module rca_tb;
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire c4;

rca uut(a,b,cin,sum,c4);

initial begin
cin = 0;
a = 4'b0110;
b = 4'b1100;
#10
a = 4'b1110;
b = 4'b1000;
#10
a = 4'b0111;
b = 4'b1110;
#10
a = 4'b0010;
b = 4'b1001;
#10
$finish();
end
                
endmodule
```
![rca4bit](https://hackmd.io/_uploads/ryqjonygA.jpg)



## Question 3
2:1 multiplexer

```verilog=
module and_gate(output a, input b, c);
assign a = b & c;
endmodule

module not_gate(output d, input e);
assign d = ~ e;
endmodule

module or_gate(output l, input m, n);
assign l = m | n;
endmodule

module m21(Y, D0, D1, S);
output Y;
input D0, D1, S;
wire T1, T2, T3;
and_gate u1(T1, D1, S);
not_gate u2(T2, S);
and_gate u3(T3, D0, T2);
or_gate u4(Y, T1, T3);
endmodule

```
testbench 

```verilog=
module mux_2_1(a,b,s0,y);
output y;
input a,b,s0;
wire w1,w2,w3;
not(w1,s0);
and(w2,w1,a);
and(w3,s0,b);
or(y,w2,w3);
    // y = S̅0 * a + S0 * b
endmodule

*Test bench*
module mux_testbench;
//inputs
 reg a;
 reg b;
 reg s0;
//output
 wire y;
    mux_2_1 uut(.a(a),.b(b),.s0(s0),.y(y)) ;
    initial begin
a=1'b0;b=1'b0;s0=1'b0;  
#2 a=1'b0;b=1'b0;s0=1'b1;    
#2 a=1'b0;b=1'b1;s0=1'b0;  
#2 a=1'b0;b=1'b1;s0=1'b1;    
#2 a=1'b1;b=1'b0;s0=1'b0;  
#2 a=1'b1;b=1'b0;s0=1'b1;  
#2 a=1'b1;b=1'b1;s0=1'b0;  
#2 a=1'b1;b=1'b1;s0=1'b1;  
end
endmodule
```
![multiplexer](https://hackmd.io/_uploads/HydrUMeg0.jpg)















