# Zbb instructions

## A.5.9. Instructions with Arguments of Two Registers.

### `count_set_bits_64`
Counts the number of set bits.

$$
ω'_D = \sum_{i=0}^{63} \mathcal{B}_8(ω_A)_i
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-cpop

### `count_set_bits_32`
Counts the number of set bits in the lower 32-bits.

$$
ω'_D = \sum_{i=0}^{31} \mathcal{B}_4(ω_A \text{ mod } 2^{32})_i
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-cpopw

### `count_leading_zero_bits_64`
Counts the number of leading (leading = starting from the most significant) zero bits.

For example:

0 => 64
1 => 63
2 => 62
3 => 62

etc.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-clz

### `count_leading_zero_bits_32`
Counts the number of leading zero bits in the lower 32-bits.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-clzw

### `count_trailing_zero_bits_64`
Counts the number of trailing zero bits.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-ctz

### `count_trailing_zero_bits_32`
Counts the number of trailing zero bits in the lower 32-bits.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-ctzw

### `sign_extend_8`
Sign-extends the lower 8-bits to 64-bits.
$$
ω'_D = \mathcal{Z}_{8}^{-1}(\mathcal{Z}_1(ω_A \text{ mod } 2^{8}))
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-sext_b

### `sign_extend_16`
Sign-extends the lower 16-bits to 64-bits.
$$
ω'_D = \mathcal{Z}_{8}^{-1}(\mathcal{Z}_2(ω_A \text{ mod } 2^{16}))
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-sext_h

### `zero_extend_16`
Clears the upper 48 bits/zero-extends the lower 16-bits to 64-bits.
$$
ω'_D = ω_A \text{ mod } 2^{16}
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-zext_h

### `reverse_byte`
Reverses the byte order of the value (endianness-swap).

For example:

`0x1234567890123456` => `0x5634129078563412`

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-rev8

## A.5.10. Instructions with Arguments of Two Registers & One Immediate.

### `rotate_right_64_imm`

Rotate $ω_A$ right by $ν_X \text{ mod } 64$.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-rori

### `rotate_right_64_imm_alt`

Rotate $ν_X$ right by $ω_A \text{ mod } 64$.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-rori

### `rotate_right_32_imm`

Rotate $ω_A \text{ mod } 2^{32}$ right by $ν_X \text{ mod } 32$ and sign extend the 32-bit result to 64 bits.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-roriw

### `rotate_right_32_imm_alt`

Rotate $v_X \text{ mod } 2^{32}$ right by $ω_A \text{ mod } 32$ and sign extend the 32-bit result to 64 bits.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-roriw

## A.5.13. Instructions with Arguments of Three Registers.

### `rotate_left_64`

Rotate $ω_A$ left by $ω_B \text{ mod } 64$.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-rol

### `rotate_left_32`

Rotate $ω_A \text{ mod } 2^{32}$ left by $ω_B \text{ mod } 32$ and sign extend the 32-bit result to 64 bits.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-rolw

### `rotate_right_64`

Same as `rotate_right_64_imm`, except takes another register instead of immediate.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-ror

### `rotate_right_32`

Same as `rotate_right_32_imm`, except takes another register instead of immediate.

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-rorw

### `and_inverted`

Like `and`, but the second argument is inverted.

$$
\forall i \in \mathbb{N}_{64} : \mathcal{B}_8(ω'_D)_i = \mathcal{B}_8(ω_A)_i \wedge \neg \mathcal{B}_8(ω_B)_i
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-andn

### `or_inverted`

Like `or`, but the second argument is inverted.

$$
\forall i \in \mathbb{N}_{64} : \mathcal{B}_8(ω'_D)_i = \mathcal{B}_8(ω_A)_i \vee \neg \mathcal{B}_8(ω_B)_i
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-orn

### `xnor`

Like `xor`, but the result is inverted.

$$
\forall i \in \mathbb{N}_{64} : \mathcal{B}_8(ω'_D)_i = \neg(\mathcal{B}_8(ω_A)_i \oplus \mathcal{B}_8(ω_B)_i)
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-xnor

### `maximum`
$$
ω'_D = \begin{cases}
ω_A &\text{if } \mathcal{Z}_8(ω_A) > \mathcal{Z}_8(ω_B)\\
ω_B &\text{otherwise}
\end{cases}
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-max

### `maximum_unsigned`
$$
ω'_D = \begin{cases}
ω_A &\text{if } ω_A > ω_B\\
ω_B &\text{otherwise}
\end{cases}
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-maxu

### `minimum`
$$
ω'_D = \begin{cases}
ω_A &\text{if } \mathcal{Z}_8(ω_A) < \mathcal{Z}_8(ω_B)\\
ω_B &\text{otherwise}
\end{cases}
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-min

### `minimum_unsigned`
$$
ω'_D = \begin{cases}
ω_A &\text{if } ω_A < ω_B\\
ω_B &\text{otherwise}
\end{cases}
$$

RISC-V reference: https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-minu