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## Chapter 6

### Register

A clocked sequential circuit consists of a group of flip-flops and combinational gates.

#### Register with Parallel Load

If all the bits of the register are loaded simultaneously with a common clock pulse, we say that the loading is done in parallel.

#### Shift Registers

A register capable of shifting the binary information held in each cell to its neighboring cell, in a selected direction, is called a shift register.

#### Serial Transfer

Information is transferred one bit at a time by shifting the bits out of the source register and into the destination register.
This type of transfer is **in contrast to** parallel transfer.

#### Serial Addition

**type 1**

The circuit adds one pair at a time through a single full-adder circuit, the carry out of the full adder is transferred to a D flip-flop.


**type 2**


#### Universal Shift Register

If the register can shift in both directions and has parallel-load capabilities, it is referred to as a universal shift register.

The most general shift register has the following capabilities:
1. A **clear** control to clear the register to 0.
2. A **clock** input to synchronize the operations.
3. A **shift-right** control to enable the shift-right operation and the serial input and output lines associated with the shift right.
4. A **shift-left** control to enable the shift-left operation and the serial input and output lines associated with the shift left.
5. A **parallel-load** control to enable a parallel transfer and the n input lines associated with the parallel transfer.
6. n parallel output lines
7. A control state that leaves the information in the register **unchanged** in response to the clock.

### Counter

A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter.

### Ripple Counters

In a ripple counter, a flip-flop output transition serves as a source for triggering other flip-flops.
In other words, the clock input of some or all flip-flops are triggered, not by the common clock pulses, but rather by the transition that occurs in other flip-flop outputs.

#### Binary Ripple Counter

An $n$-bit binary counter consists of $n$ flip-flops and can count in binary from $0$ through $2^n-1$.

**Binary countdown counter**
the binary count is decremented by 1 with every input count pulse.

#### BCD Ripple Counter

A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9.

### Synchronous Counters

In a synchronous counter, the clock inputs of all flip-flops receive the common clock.

#### Binary Counter

The flip-flop in the least significant position is complemented with every pulse.
A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1.

**Up-Down Binary Counter**

A bit in any other position is complemented if all lower significant bits are euqal to 0.

#### BCD Counter

just do the state table shit, hell yeah dude.

**Binary Counter with Parallel Load**

Counters employed in digital systems quite often require a parallel-load capability for transferring an initial binary number into the counter prior to the count operation.

possible operations:
1. clear to 0
2. load inputs in parallel
3. count next binary state
4. no change

### Other Counters

something like divide-by-$N$ counter (modulo-$N$ counter)

#### Counter with Unused States

A counter that use fewer than $2^n$ states.

#### Ring Counter

A circular shift register with only one flip-flop being set at any particular time.

e.g.
0001 $\rightarrow$ 0010 $\rightarrow$ 0100 $\rightarrow$ 1000 $\rightarrow$ repeat

#### Switch-tail Ring Counter

A circular shift register with the complemented output of the last flip-flop connected to the input of the first flip-flop.

e.g.

000 $\rightarrow$ 001 $\rightarrow$ 011 $\rightarrow$ 111 $\rightarrow$ 110 $\rightarrow$ 100 $\rightarrow$ repeat

#### Johnson Counter

Identical to switch-tail ring counter in some definitions.

A Johnson counter is a $k$-bit switch-tail ring counter with $2k$ decoding gates to provide outputs for $2k$ timing signals.

e.g.

| state | output |
| ----- | ------ |
| 000 | 0 |
| 001 | 1 |
| 011 | 2 |
| 111 | 3 |
| 110 | 4 |
| 100 | 5 |

## Chapter 7

### Random Access Memory(RAM)

The time it takes to transfer information to or from any desired random location is always the same.

#### Operations

| Memory Enable | Read / Write | Memory Operation |
| ------------- | ------------ | ---------------------- |
| 0 | X | None |
| 1 | 0 | Write to selected word |
| 1 | 1 | Read to selected word |

#### SRAM

A SRAM binary cell is often an electronic circuit with four to six transistors.

#### DRAM

The DRAM cell contains a single MOS transistor and a capacitor.
The charge stored on the capacitor discharges with time, and the memory cells must be periodically recharged by refreshing the memory.

### Words

A word in memory is a set of bits that move in and out of storage as a unit.

### Suffixes

It is customary to refer to the number of words (or bytes) in memory with one of the letters K (kilo), M (mega), and G (giga).

| Suffix | number |
| ------ | -------- |
| K | $2^{10}$ |
| M | $2^{20}$ |
| G | $2^{30}$ |

### Binary storage cell (BC) / memory cell

A binary storage cell must be very small in order tobe able to pack as many cells as possible in the small area available in the integrated circuit chip.

### Coincident Decoding

e.g.

Instead of using a single 10 $\times$ 1024 decoder, we use two 5 $\times$ 32 decoders.

### Error Detection and Correction

#### Hamming Code

In Hamming code, $k$ parity bits are added to an $n$-bit data word, forming a new word of $n+k$ bits.

e.g. 8-bit data

**Form**

| Bit position | Value |
| ------------ | ----- |
| **1** | $P_1$ |
| **2** | $P_2$ |
| 3 | $D_1$ |
| **4** | $P_4$ |
| 5 | $D_2$ |
| 6 | $D_3$ |
| 7 | $D_4$ |
| **8** | $P_8$ |
| 9 | $D_5$ |
| 10 | $D_6$ |
| 11 | $D_7$ |
| 12 | $D_8$ |

$P_1=\text{XOR of bits}(3,5,7,9,11)$
$P_2=\text{XOR of bits}(3,6,7,10,11)$
$P_4=\text{XOR of bits}(5,6,7,12)$
$P_8=\text{XOR of bits}(9,10,11,12)$

**Check**

Do 4 parity check as following:

$C_1=\text{XOR of bits}(1,3,5,7,9,11)$
$C_2=\text{XOR of bits}(2,3,6,7,10,11)$
$C_3=\text{XOR of bits}(4,5,6,7,12)$
$C_4=\text{XOR of bits}(8,9,10,11,12)$

$C=C_8C_4C_2C_1$

if $C\neq 0000$, error occurred, and can be fixed by complementing the corresponding bit.

**Single-Error Correction, Double-Error Detection**

Add an additional parity bit on top of Hamming code.

### Read-Only Memory (ROM)

A read-only memory is essentially a memory device in which permanent binary information is stored.

#### Mask Programming

Done by the semiconductor company during the last fabraication process of the unit.
Only if a large quantity of the same ROM configuration is to be ordered.

#### Programmable Read-Only Memory (PROM)

When ordered, PROM units contain all the fuses intact, giving all 1's in the bits of the stored words.
Special instruments called PROM programmers are available commercially to facilitate the procedure.

#### Erasable PROM (EPROM)

When the EPROM is placed under a special ultraviolet light for a given length of time, the shortwave radiation discharges the internal floating gates that serve as the programmed connections.

#### Electrically EPROM (EEPROM, E$^2$PROM)

This device is like the EPROM, except that the previously programmed connetions can be erased with an electrical signal instead of ultraviolet light.
The device can be erased without removing it from the socket.

**However, it is subject to fatigue.**

#### Flash memory devices

Similar to EEPROMs, but have additional built-in circuitry to selectively program and erase the device in-circuit, without needing a special programmer.

**However, it is subject to fatigue.**

### Combinational Programmable Logic Devices (PLDs)

#### PROM

Inputs
$\rightarrow$ Fixed AND array (decoder)
$\rightarrow$ **programmable OR** array
$\rightarrow$ Outputs

#### Programmable Array Logic (PAL)

Inputs
$\rightarrow$ **programmable AND** array
$\rightarrow$ Fixed OR array
$\rightarrow$ Outputs

simplificate to **minimum number of terms by the funciton itself**

##### PAL Programming Table

e.g.


#### Programmable Logic Array (PLA)

Inputs
$\rightarrow$ **programmable AND** array
$\rightarrow$ **programmable OR** array
$\rightarrow$ Outputs

simplificate to **minimum number of terms among all the functions**

##### PLA Programming Table

e.g.


### Sequential Programmable Devices

Since the combinational PLD consists of only gates, it is necessary to include external flip-flops when they are used in the design.

**Types**

1. Sequential(or Simple) programmable logic device (SPLD).
2. Complex programmable logic device (CPLD)
3. Field-programmable gate array (FPGA)

#### SPLD

##### macrocell

Each section of an SPLD is called a macrocell, which is a circuit that contains a sum-of-products combinational logic function and an optional flip-flop.

#### FPGA

not included