---
# System prepended metadata

title: Digital Circuit Design MP#3
tags: [homework]

---

---
tags: homework
---

# Digital Circuit Design MP#3

## Verilog Code

### Explanation

```verilog
    wire [3:0] h0 ; 
    wire [2:0] h1 ;

    BCD_counter H0 (h0, h0_tc, clr_, m1_tc, clk) ;
    Hex_counter H1 (h1, h1_tc, clr_, h0_tc, clk) ;
```

counter for hours

```verilog
        repeat(2*60*25)
```

extend to 25 hours

```verilog
    always@(h0 or h1)
        if (h1 >= 2 && h0 >= 4)
            clr_ = 0;
```

when the time past 24 hours, reset the counters

```verilog
    always@(clr_)
        #3 clr_ = 1'b1;
        
    initial
    begin
      clr_ = 0;
    end
```

let the clr switch automatically turn off after a short period of time

### Full code


```verilog
`timescale 100ms/10ms

module BCD_counter(count,TC,clr_, enb, clk) ;
    output [3:0] count ;
    output TC ;
    reg [3:0] count ;
    input clr_, enb, clk ;
    reg TC ;

    always @ (*)
        if(enb && count >= 9)
            TC = 1;
        else
            TC = 0;

    always @ (posedge clk or negedge clr_) // combinational+sequential
        if (~clr_)
            count = 0 ;
        else if (enb)
            if (TC)
                count = 0;
            else
			count = count + 1;
endmodule

module Hex_counter(count,TC,clr_, enb, clk) ;
    output [2:0] count ;
    output TC ;
    reg [2:0] count ;
    input clr_, enb, clk ;
    reg TC ;

    always @ (*)
        if(enb && count >= 5)
            TC = 1;
        else
            TC = 0;	


    always @ (posedge clk or negedge clr_) // combinational+sequential
        if (~clr_)
            count = 0 ;
        else if (enb)
            if (TC)
                count = 0;
            else
                count = count + 1 ;
endmodule


module Testfixture;
    wire Vdd = 1'b1;
    reg clk, clr_;
    wire [3:0] m0 ;
    wire [2:0] m1 ;
    wire [3:0] h0 ; 
    wire [2:0] h1 ;

    BCD_counter M0 (m0, m0_tc, clr_, Vdd, clk) ;
    Hex_counter M1 (m1, m1_tc, clr_, m0_tc, clk) ;

    BCD_counter H0 (h0, h0_tc, clr_, m1_tc, clk) ;
    Hex_counter H1 (h1, h1_tc, clr_, h0_tc, clk) ;

    //Stimulus
    initial
    begin
        clk = 1'b0 ;
        repeat(2*60*25)
            #5 clk = ~clk ;
        $finish ;
    end

    always@(h0 or h1)
        if (h1 >= 2 && h0 >= 4)
            clr_ = 0;

    always@(clr_)
        #3 clr_ = 1'b1;
        
    initial
    begin
      clr_ = 0;
    end

    initial
    begin
        $dumpfile("Clock.vcd");
        $dumpvars;
    end

endmodule
```


## GTKWave Screenshot

![](https://hackmd.io/_uploads/Bk4ukSHN2.png)
