---
tags: homework
---

# Digital Circuit Design MP #1

## Verilog Code

`timescale 1ns/10ps
module test_mux ;

reg a, b, sel, out;

// RTL modeling
    always @(a or b or sel)
    if(sel)
        out = b;
    else 
        out = a;

//Stimulus
    initial
    begin
          a=0 ; b=1 ; sel=0 ;
      #5  b=0 ;
      #5  b=1 ; sel=1 ;
      #5  a=1 ;
      #5  b=0 ;
    end

    //Display results
    initial
    begin
      $display("                time out  a   b  sel");
      $monitor($time, "  %b   %b   %b   %b", out,a,b,sel) ;
    end

        initial
        begin
    $dumpfile("mux_t.vcd");
    $dumpvars;
        end

endmodule

## Timing Diagram


> ID: 111550013
> Name: 施羿廷