# Deep Learning Process Integration on Heterogeneous GPU/FPGA Embedded Platforms _by Walther Carballo Hernández (Institut Pascal, Fr) - 2023.01.24_ ###### tags: `VAADER` `Seminar` ![](https://i.imgur.com/tE2CPrV.png) ## Abstract Deep Learning (DL) algorithm deployment on edge devices, such as Convolutional Neural Network (CNN) inference, has established a high computing demand on devices with limited resources, requiring low execution time and reduced energy consumption. To meet the requirements with such constraints, hardware systems have adopted unconventional processors co-located on the same platform. This architectural heterogeneity introduces many challenges in how these processors interact. A well-defined software-hardware co-design environment must be carefully built to ensure a high-performance solution. For this purpose, heterogeneous hardware-awareness must be integrated in the design workflow. To avoid hardware-agnostic low performance programming, state-of-the-art literature incorporates performance profiling models to aid with partition selection on each accelerator. Subsequently, mathematical optimization techniques benefit from these models to improve workload distribution, specifically tailored for the platform. This seminar talk aims to assist the designer by studying the modeling, partitioning and optimization of embedded heterogeneous platforms in the context of CNN computation models. The scope of this presentation mainly covers the coupling topologies between Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA) accelerators in hybrid systems. The opportunities and limitations of hybrid programmable logic and Single Instruction Multiple Data (SIMD) architectures are analyzed and discussed.