PCS - HackMD

# PCS ## Lab0 1) lees sim.out - vershil instructions and micro-ops - frequency of simulated processor (cycles/time) ``` Cycles 54786355 Time (ns) 20596374 ~= 0.276 GHz ``` - IPC ``` Instructions 9999955 Cycles 54786355 ~= 0.18 IPC ``` - µPC ``` Micro-ops 11020547 Cycles 54786355 ~= 0.20 µPC ``` 2. The width is a lot larger than the µPC, this is not what you'd expect, but this is due to a bottleneck elsewhere 3. The largest CPI component is the memory dram, it is very logical that memory is the bigest limiter. We might consider increasing the caches to solve this. ``` CPI Time base 0.14 2.54% branch 0.09 1.67% mem-l1d 0.08 1.51% mem-dram 5.02 91.64% other 0.14 2.64% total 5.48 100.00% ``` 4. L2 and L3 cache misses (±80% and ±62%) ``` Cache Summary | Cache L1-I | num cache accesses | 1075571 num cache misses | 2712 miss rate | 0.25% mpki | 0.27 Cache L1-D | num cache accesses | 3884470 num cache misses | 1411875 miss rate | 36.35% mpki | 141.19 Cache L2 | num cache accesses | 1538400 num cache misses | 1241756 miss rate | 80.72% mpki | 124.18 Cache L3 | num cache accesses | 1366224 num cache misses | 842984 miss rate | 61.70% mpki ``` 5.