---
# System prepended metadata

title: Lab 8

---

# Lab 8
Name: SUDDULA VINEETH RAGHAVENDRA
Roll No.: CS22B045

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## Question 1
**Verilog Code of Full Adder by using Two Half Adders.**

```
module half_adder (a,b,sum,carry);
input a,b;
output sum,carry;
assign sum = a^b;
assign carry = a&b;
endmodule
```

```
module full_adder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
wire c,c1,s;
half_adder ha0(a,b,s,c);
half_adder ha1(cin,s,sum,c1);
assign carry = c | c1 ;
endmodule
```

```
module full_adder_testbench;
reg a,b,cin;
wire sum,carry;
full_adder uut(a,b,cin,sum,carry);
initial begin
a = 0; b = 0; cin = 0;
#10
a = 0; b = 0; cin = 1;
#10
a = 0; b = 1; cin = 0;
#10
a = 0; b = 1; cin = 1;
#10
a = 1; b = 0; cin = 0;
#10
a = 1; b = 0; cin = 1;
#10
a = 1; b = 1; cin = 0;
#10
a = 1; b = 1; cin = 1;
#10
end    
endmodule
```

---

## Question 2

**Verilog Code of Ripple Carry Adder**

```
module full_adder(input a,b,cin,output sum,carry);
assign sum = a ^ b ^ cin;
assign carry = (a & b)|(b & cin)|(cin & a);
endmodule
```

```
module rca( // this is the code for ripple carry adder.
    input [3:0]a,b,
    input cin,
    output [3:0]sum,
    output c4);
wire c1,c2,c3;      //Carry_out of the each full adder
full_adder fa0(a[0],b[0],cin,sum[0],c1);
full_adder fa1(a[1],b[1],c1,sum[1],c2);
full_adder fa2(a[2],b[2],c2,sum[2],c3);
full_adder fa3(a[3],b[3],c3,sum[3],c4);     
endmodule
```

```
module rca_tb; // this is the code for the testbench.
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire c4;
rca uut(a,b,cin,sum,c4);
initial begin
cin = 0;
a = 4'b0110;
b = 4'b1100;
#10
a = 4'b1110;
b = 4'b1000;
#10
a = 4'b0111;
b = 4'b1110;
#10
a = 4'b0010;
b = 4'b1001;
#10
$finish();
end            
endmodule
```

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## Question 3
**Verilog Code of 2:1 Multiplexer**

```
module mux_2x1( // code for multiplixer.
input I0,I1,S,
output Y);
assign Y = S?I1:I0;   
endmodule
```

```
module mux_tb; // code for test bench.
reg I0,I1,S;
wire Y;
mux_2x1 uut(I0,I1,S,Y);
initial begin
S = 0; I0 = 1; I1 = 0;
#10
I0 = 0; I1 = 1;
#10
S = 1; I0 = 1; I1 = 0;
#10
I0 = 0; I1 = 1;
#10
$finish();
end              
endmodule
```

---





